The Xfuzzy 3 development environment
The VHDL code generation tool - Xfvhdl
The tool xfvhdl uses the high level hardware description language VHDL to facilitate the hardware implementation, through FPGAs or ASICs, of inference systems described in the Xfuzzy environment. An important feature of this tool is that it allows the direct synthesis of complex fuzzy systems, composed by the combination of different inference modules and crisp blocks. However, not all XFL3 specifications are able to be implemented in hardware through xfvhdl. In particular, fuzzy systems that can be implemented by this tool must use membership functions with maximum overlap 2 and use simplified defuzzification methods.
The graphical user interface of xfvhdl can be executed from the main window of the environment, using the "To VHDL" option in the Synthesis menu, or from the command line, by means of the expression "xfvhdl -g file.xfl [file.xml]".
The main window of xfvhdl is divided into four parts. The upper area collects information about the files and directories involved in the design. The Input XFL file field contains the absolute path of the XFL3 specification file selected when the tool is launched. This field is only informative, that is, it is not modifiable by the user. The Name for output files field allows to configure the prefix of the output files. By default, the name of the input fuzzy system appears, although it can be modified by the user. Finally, the Output directory field indicates the absolute path of the directory where the output files generated by the tool will be located. Its default value is the directory that contains the system specification.
The lower area of the window contains three sections that allow defining different synthesis and implementation options. In the Global options section, the user can select to generate additional files by checking the Generate complementary files option. He can also select the use of simplified components through the Use simplified components option. When this option is chosen, the simplified version (without division block) for Fuzzy Mean and Takagi-Sugeno defuzzifiers will be included in the VHDL description, as long as the system specification allows it (systems with standard membership functions using the product operator as antecedent connective; the tool will obviate the use of simplified components in cases where these conditions are not verified, even if the option is selected). Finally, when the Files for Hardware Simulation option is selected, the tool generates output VHDL descriptions adapted to be incorporated into Simulink models through the use of "Black Boxes". The FPGA Implementation section collects information regarding implementation options for FPGAs. Among them, the type of RAM and ROM to be used (initially the option Automatic appears in both, although a drop-down menu also allows selecting the options None, Block or Distributed), as well as the family of FPGAs and the device used to implement the inference system (the default choice is Zynq xc7z020-clg484-1). Finally, the CAD Tool Options section includes a set of options related to CAD tools. Among them: the synthesis tool to be used (the default option is Xilinx Vivado, although Xilinx XST can also be selected); the type of optimization (the preselected option is Without optimization, but the options Area optimization, Speed optimization and Area and Speed optimizations can also be selected in the menu); and the effort with which the synthesis is carried out (the Low option is selected a priori, although the High option can also be chosen in the drop-down menu).
The central area of the window is in turn divided into two parts. Initially, the graphical representation of the XFL3 specification appears on the right, while, on the left, the different knowledge base components are structured in a tree and grouped under RuleBases and CrispBlocks categories. When a specific rule base is selected, the content of the right central area is replaced by a new interface that allows to define parameters related to system dimension. Specifically, the number of bits to encode inputs, output, membership degrees of the antecedents, slopes of the membership functions, and weight parameter of the defuzzification method (in cases where this exist) can be defined. Also in this area can be selected the implementation strategy for antecedents (in memory or by arithmetic calculation) and the type of memory used (ROM, RAM or logical block). The tool allows the generation of standardized membership functions of triangular, sh_triangular, and trapezoid types by means of arithmetic techniques. In the event that input membership functions are not normalized, the arithmetic calculation option for antecedents is disabled. For the rule memory can also be chosen to implement they with ROM, RAM or logical blocks. In the lower part of this area, information extracted from the XFL3 specification related to membership functions and rule bases is shown. Specifically, this area includes the values of the number of membership functions, breakpoints and slopes for each input, as well as the matrix representation of the corresponding rule base. The values shown are for informational purposes only, so they cannot be modified.
When selecting a crisp block within the tree structure, a single field related to the number of bits with which the output of the block is encoded appears in the right central area.
When all the architectural options and the parameters related to the size of the buses corresponding to a rule base have been defined, this configuration must be assigned by means of the Apply button (located in the lower part of the window). After that, the red icon that appeared next to the knowledge base in the first figure is replaced by the green icon that can be observed in the second. Once the information corresponding to all the rule bases and crisp blocks of the system has been defined, the component associated to the fuzzy system is also identified with a green mark and the buttons Save Configuration, Generate VHDL code and Generate and Implement are activated.
The Save Configuration button allows saving the system configuration through an XML file that stores information related to the implementation options of the different components (see section Configuration file). Configurations saved with this approach can be loaded later using the Load Configuration button or used to run the tool in non-interactive mode (see section Execution in command mode).
The Generate VHDL code button generates the VHDL description of the fuzzy system together with a testbench file, also described in VHDL, which allows verifying its functionality. The VHDL description of the system is generated in a single file composed of the interconnection of blocks from the XfuzzyLib cell library . The header of this file also includes a package of constants automatically calculated from the information extracted from the knowledge base of the inference system and from the parameters and design options introduced by the designer. For hierarchical systems, a VHDL description is generated for each rule base, as well as a testbench that allows obtaining the control surface corresponding to each of them. In this case, a VHDL file corresponding to the upper level of the hierarchy (top-level) is also generated, which describes the interconnection of the different rule bases and crisp blocks that make up the system, as well as a testbench that allows to simulate the whole system.
In addition to the above files, if the selected synthesis tool is Xilinx Vivado, two command files with
extension ".tcl" are generated. The file "
When the selected tool is Xilinx XST, two additional files with ".prj" and ".xst" extensions are generated.
The file "
Finally, if the option to generate complementary files have been selected, a series of files with extensions ".dat", ".dat.bin" and ".plt" are generated. These files contain information related to the content of the antecedent memories and the rule bases of the system for further study. A file ".dat" and another ".dat.bin" are generated for each input variable, which contain the data from the antecedent memories (combinations of label-grade-grade values) in decimal and binary formats, respectively. The file ".plt" is a Gnuplot command file that allows to graphically represent the membership functions. Finally, the file with extension ".dat" includes the content of the rule memory.
During the generation of the files, there may be errors or warnings that will be communicated to the user in the Xfuzzy message area. The list of errors, together with the description of the causes that motivate them, is illustrated in the error messages section.
The Generate and Implement button generates the same files as the Generate VHDL code button, but also synthesizes the VHDL code and implements it on the Xilinx FPGA specified in FPGA implementation, with the implementation options specified in Cad Tools Options, making use of Xilinx synthesis and implementation tools. In this phase, the message "There are errors, so cannot execute any synthesis tool" or "There are errors, so cannot execute any implementation tool" may appear if some error has previously occurred in the creation files stage.
The xfvhdl tool can also be run from a terminal using the following commands:
-I: (generates VHDL code, synthesizes and implements)
-L <library>: (use the indicated VHDL library, instead of using the default one)
The configuration of the synthesis process with xfvhdl can be saved in an XML file. The root of the configuration file is the label called system, which has three attributes: name, rulebases and crisps. The first indicates the name of the system, while the other two indicate, respectively, the number of rule bases and crisp blocks.
The file includes three main elements: rulebases, crisps and options. The rulebases tag contains information about the rule bases, each of them identified with the rulebase tag. This element has as attributes: name, which indicates the name of the rule base; inputs, which indicates the number of inputs; and outputs, which indicates the number of outputs. The child elements of this tag define each of the parameters of the rule base: bits_input (number of bits for the inputs), bits_output (number of bits for the outputs), bits_membership_degree (number of bits for the membership degree), bits_MF_slopes (number of bits for slopes), bits_def_weight (number of bits for the weight of the defuzzifiers that use this parameter), MFC_arithmetic (boolean indicating whether the MFCs were chosen to be implemented by arithmetic circuits (true) or by means of memory (false)), MFC_memory (indicates the type of memory chosen for the antecedent memory) and RB_memory (indicates the type of memory chosen for the rule memory).
The crisps element appears empty when the system does not include any block of this type. Otherwise, each block is defined by a crisp tag that includes the attributes: name, which indicates the name of the block; inputs, which indicates the number of inputs; and outputs, which indicates the number of outputs. The only parameter that can be defined for this type of elements is the number of bits used to encode the output (bitsize_output).
Finally, the options tag is used to identify the different options that appear at the bottom of the graphical user interface of xfvhdl. The child elements of this tag are: complementary_files (boolean that indicates whether the user selects the option to generate complementary files), use_simp_components (boolean that shows whether the user selects the option to use simplified defuzzification methods, FPGA_RAM (number from 0 to 3 which indicates the type of RAM used, 0=Automatic, 1=None, 2=Block, 3=distributed), FPGA_ROM (number from 0 to 3 that indicates the option chosen for the ROM used, 0=Automatic, 1=None, 2=Block, 3=distributed), FPGA_family (text indicating the family of FPGAs chosen by the user), CAD_tool (number 0 or 1 indicating the chosen synthesis tool, 0=Xilinx Vivado, 1=Xilinx XST), CAD_optimization (number from 0 to 3 indicating the optimization to be used, 0=Without optimization, 1=Area optimization, 2=Speed optimization, 3=Area and Speed optimization), and CAD_effort (number 0 or 1 indicating the synthesis effort, 0=Low, 1=High).
-------------------------------------------------------------------------------------- M. Brox, S. Sánchez-Solano, E. del Toro, P. Brox, F. J. Moreno-Velo CAD Tools for Hardware Implementation of Embedded Fuzzy Systems on FPGAs IEEE Transactions on Industrial Informatics, 2012 DOI: 10.1109/TII.2012.2228871
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