ESR3: UCA
Towards Low Energy Smart Cameras
@ Institut Pascal (CNRS-Université Clermont Auvergne), France
A smart camera is fundamentally a Cyber-Physical System where computation is entangled with visual sensor information and network communication. Moreover, the high throughput data provided by image sensors makes low energy smart camera design particularly challenging. System-level optimization the only short-term candidate to obtain the energy efficiency gain needed to reach Low Energy Smart Cameras. This research project will consist in designing and prototyping a low energy smart camera while building innovative system-level design methods that predict and optimize energy, based on separated Model of Computation (MoC) and Model of Architecture (MoA) and on matching at system level.
Walther Carballo Hernández
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BIOGRAPHY Walther Carballo Hernández was born in the city of Veracruz, Mexico. He obtained a Bachelor degree of Electronic Technologies Engineering from the Institute of Technology of Superior Studies of Monterrey (ITESM) in Puebla, Mexico (2007-2012). Afterwards, he obtained a Master degree of Intelligent Systems from the same Institute while working as Research and Development software and hardware engineer at French-Mexican Company ProBayes Americas (2012-2015). Immediately after, he pursued a career as early-stage researcher in Computer Science at the National Institute of Astrophysics, Optics and Electronics (INAOE) in Puebla, Mexico (2016-2018). At the same time he started an academic career as Associate Professor at ITESM University in the area of Computer Science and Electronic Engineering (2016-2017). He is currently an early stage researcher and PhD student as part of the DREAM team of the Image, Perception Systems and Robotics (ISPR) in the Institut Pascal, affiliated with the University Clermont Auvergne (UCA). |
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Walther.Carballo_Hernandez@uca.fr
@WaltherCarballo
linkedin.com/in/walther-carballo-hernández
MY PROJECT
"Deep Learning Process Integration on Heterogeneous FPGA/GPU Platform"
TASK
- State-of-the-art review as part of a Survey comparing multiple Heterogeneous platforms (FPGA/GPU/CPU/ASIC) for Deep Learning inference processes in a computer vision context using Convolutional Neural Networks.
- Metric selection for performance and efficiency comparison on a FPGA/GPU platform.
- DL software libraries integration and model partitioning and compression techniques.
- Software tool analysis for Heterogeneous Hardware development: Generic (eg. OpenCL) or specific tools (eg. VHDL, Verilog, CUDA).
Experimental methodology definition for hardware space exploration, resources utilization, performance and efficiency based on selected metrics.
EXPECTED RESULTS
From a hardware perspective: A low-power consumption and efficient performance integration of Deep Convolutional Neural Networks models for inference acceleration on embedded heterogeneous FPGA/GPU platforms. From software perspective: A theoretical validation for model partitioning and workload balancing using mixed low-precision quantizing and retaining high-precision when required, where each architecture can excel at its dedicated task.