IEEE CEDA Spain Chapter / NANOVAR Workshop

The Spain Chapter of the IEEE Council on Electronic Design Automation (CEDA)  and the NANOVAR Network of Excellence present the workshop:

Title: How to survive in an unreliable world

Date: November 21, 2017

Time: 9:00-17:30 CET

Venue: Escola d'Enginyeria de Barcelona Est (EEBE), UPC Campus Diagonal-Besòs, Barcelona, Spain.

Registration: Registration required by November 15. No registration fee. Register at

Activity supported by Universitat Politècnica de Catalunya

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Presentation IEEE CEDA Spain Chapter and NANOVAR network

Montserrat Nafría / Francisco V. Fernández-José Luis Ayala


Opening lecture

Lifetime simulation of semiconductor circuits

Dr. Linda Milor

Georgia Tech



Modeling of unreliability effects in electronic devices

Dr. J. Martin-Martinez



Reliability in the circuit design flow: from characterization and modelling to design automation

Dr. R. Castro-López






Benefactory factors of noise and degradation in the performance of non-linear circuits

Dr. A. Rubio



Exploiting the variability of semiconductor fabrication process for hardware security

Dr. I. Baturone






Robust design based on variability monitoring 

Dr. M. Lopez Vallejo



Transient Radiation effects on SRAM memories

Dr. G. Torrens






Why is systematic AMS-RF test not there yet?

Dr. G. Leger



Test and fault diagnosis in digital circuits

Dr. R.  Rodriguez



Detailed contents

Opening lecture

Title:  Lifetime simulation of semiconductor circuits

Authors: Prof. Linda Milor


Technology scaling has resulted in higher operating temperatures and electrical fields, and this has contributed to faster device and interconnect aging. As a result, wearout has become a more important problem.

Technology qualification and monitoring for reliability involves checking the lifetime of test structures, together with area scaling and scaling to use conditions, to project the lifetime of a full chip from that of a test structure, tested under accelerated conditions. These methods to link the lifetime of a test structure to a circuit do not take into account the details of operation. Our work aims to include operating details in lifetime estimates. We consider a wide variety of wearout mechanisms, including bias temperature instability, hot carrier injection, gate oxide breakdown, backend dielectric breakdown, electromigration, and stress-induced voiding. For wearout mechanisms associated with sudden and hard breakdown, we link process-level lifetime models of layout features to operating conditions (determined by system emulation with benchmarks). The feature-level lifetime models are combined to estimate system lifetime (with and without redundancy). For wearout mechanisms associated with gradual degradation, we determine the statistical distribution of the time when circuit performances fail, taking into account the performance requirements and operating conditions.


Talk #1

Title:  Modeling of unreliability effects in electronic devices

Authors: J. Martin-Martinez, R. Rodríguez, M.Nafría


Time Dependent Variability (TDV) in scaled CMOS technologies provokes uncertainty in the electrical characteristics of transistors that will be transferred to the circuit performance. Therefore, understanding the phenomenology behind TDV is fundamental to explore new techniques that allow the design of reliable circuits. Several mechanisms are the main responsible of TDV in current and future technologies. In this talk, the physical origin of the main mechanisms (Random Telegraph Noise, Bias Temperature Instabilities and Channel Hot Carriers) will be reviewed. The latest advances in the device TDV physics-based compact modeling will be also addressed.


Talk #2

Title:  Reliability in the circuit design flow: from characterization and modelling to design automation

Authors: R. Castro-López, J. Díaz, J. Martín-Martínez, R. Rodríguez, M. Nafría,  A. Toro, P. Martín, E. Roca, F.V. Fernández, E. Barajas, X. Aragonés, D. Mateo


Designing reliable analog circuits in advanced process technologies requires an accurate understanding of both device performance and variability. The unavoidable and increasingly important process-induced variations is, today, not alone in perturbing the ideal, intended performance of analog circuits: the so-called aging phenomena, like Bias Temperature Instability and Hot Carriers Injection, are altogether making the analog design business a much more tortuous endeavour. 
The work presented here will paint a complete picture of how to deal with variability in analog circuits for advanced process technologies. This picture starts with the characterisation and modelling of the aging phenomena at the device level. It then will show how these models can be used in the simulation of analog circuits, explaining the issues to overcome and the solutions that can be adopted. With these accurate models and capable circuit simulation techniques, the picture ends with a proposal for an analog design methodology that, using advanced optimization techniques, can successfully take into accounts all sources of variations (process and aging related) so that reliable analog circuits can be attained.


Talk #3

Title:  Benefactory factors of noise and degradation in the performance on non-linear circuits

Authors: A. Rubio


The work of engineers has been always mainly framed to the design and implementation of robust circuits and systems operating in the presence of undesired evils of nature as temperature, deviations, noise and degradation. However, in social and living as well as in artificial non-linear systems these factors have been shown to be benefactors in many cases producing significant advantages in elements built including them. The talk will cover areas where the active use of these unwanted factors produce demonstrated profits in the behavior or performances of the system. Temperature effects in biological and electronic systems, the advantages of not only not avoiding but also inserting noise in certain systems will be visited showing a possible increase of sensitivity, gain, and reliability. Advantages of variability and aging will also been exposed in other specific situations.


Talk #4

Title:  Exploiting the variability of semiconductor fabrication process for hardware security

Authors: I.  Baturone , P. Brox, R. Arjona and M.A. Prada-Delgado


Variability of semiconductor fabrication process can be a problem for many electronic designers, but it is a strength for many others who want to increase the security of electronic products. This talk summarizes how to exploit variability to provide, from hardware, identifiers and cryptographic primitives such as secret keys and true random numbers and, hence, how hardware-based security can solve vulnerabilities of software-based security.


Talk #5

Title:  Robust design based on variability monitoring 

Authors: M. Lopez Vallejo and P. Ituero


Current nanometer technologies suffer within-die parameter uncertainties, varying workload conditions, aging, and temperature effects that cause a serious reduction on yield and performance. In this scenario, monitoring, calibration, and dynamic adaptation become essential, demanding systems with a collection of multi purpose monitors and exposing the need for light-weight monitoring networks. This talk presents how the use of  proactive approaches to reliability becomes a must. Designers should develop architectures adaptable to variations of all kinds, which rely heavily on information gathered from in situ monitoring circuits. Multiuse sensors that can monitor performance, degradation, temperature or power consumption as the circuit ages are critical. Their allocation and connection with reduced area overhead is also a challenge for designers when working with deep nanometer technologies Monitoring: a lifeboat in a varying environment.


Talk #6

Title:  Transient Radiation effects on SRAM memories

Authors: G . Torrens, S. Bota and J. Segura


The design and implementation of faster, more complex and compact systems, has been greatly benefited by the development of modern microelectronic nanometer technologies. This progress has been possible thanks to the decrease of supply voltage and aggressive technology scaling, which as a collateral effect has led to new mechanisms contributing to device reliability issues. In this way, ionizing radiation effects are not a specific problem exclusively related to space or avionic applications anymore and have become a major concern for reliability and dependability of emerging electronic devices. Ionizing particles may interact with silicon and produce disturbing transient currents at a circuit node causing Single Event Upset (SEU) in memory cells,. These phenomena and its impact on memory design will be discussed.


Talk #7

Title:  Why is systematic AMS-RF test not there yet?

Authors: G. Leger and M. Barragán


For many years, both the academy and the industry have been pursuing the goal of systematic, and possibly automated, AMS-RF test. Many approaches tried to parallel what had been successful for digital circuit, where test considerations are fully embedded in the design flow.  In this talk, we will briefly review what has been done in the field of AMS-RF test, what is the current state-of-the-art and finally, we will try to point out what is the major bottleneck for systematic test methodologies.


Talk #8

Title:  Test and fault diagnosis in digital circuits

Authors: R.  Rodriguez


Testing and diagnosis are key issues in the semiconductor fabrication process. Each one of the manufactured chips needs to be tested in order to assure the non-presence of defects so as correctly functioning integrated circuits are sold to the customer. Traditionally, the test is done on automated test equipment by applying test patterns to check for a set of previously selected faults. In addition, chips that fail during testing need to be diagnosed to determine the cause of the failure so that the manufacturing process can be improved to increase the yield. With the increase in size and complexity of the integrated circuits even on a 3D dice mounting and the big impact of process parameters, the test and diagnosis is becoming a challenging and time-consuming process. A review of the main concepts about realistic defects, fault models and basic types of testing and diagnosis will be presented for digital integrated circuits together with the main challenges faced by them in the future.

Presentation of IEEE CEDA Spain Chapter and Panel Session at DCIS 2017

The IEEE CASS and CEDA Spain Chapters sponsor the DCIS2017 Panel Session:

Title: Finishing your PhD? And now what?

Date: November 22, 2017

Venue:  Escola d'Enginyeria de Barcelona Est (EEBE), UPC Campus Diagonal-Besòs

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Moderators: Antonio López (CASS Spain Chair-Elect), Francisco V. Fernández (CEDA Spain Interim Chair)


       David Atienza (École Polytechnique Fédérale de Lausanne, Switzerland)

       Ignasi Cairó (Witeklab SL, Spain)

       Richard Gaggl (Infineon Technologies, Germany)

       Jaime Ramírez Angulo (New Mexico State University, USA)

       Josep Samitier (Instituto de Bioingeniería de Cataluña, Spain)

       Lluis Terés (Instituto de Microelectrónica de Barcelona, Spain)


The panel will be preceded by the Presentation of the IEEE CEDA Spain Chapter with the participacion of David Atienza (CEDA President-Elect), Francisco V. Fernández (CEDA Spain Interim Chair), José L. Ayala (CEDA Spain Interim Vice-chair).

Talk by IEEE Distinguished Lecturer Prof. Giovanni de Micheli

Title: New horizons for electronic systems: Devices, design methods and application areas

Date: November 3, 2017

Time: 12:00 CET

Venue: Sala de Grados of Facultad de Informática. Universidad Complutense de Madrid.

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Prof. de Micheli will talk about his research work and will provide a broader view of today’s Electronic Systems. In that matter, he will show the current landscape of distributed computing and will cover the most recent technological innovations, part of them related to emerging nanotechnologies and devices.

Prof. de Micheli will also present the available tools for design with emerging technologies, like physical and logic synthesis tools. Going deep in this topic, we will have the chance to revisit the majority paradigm in logic synthesis, for models, algorithms and tools.


Giovanni De Micheli is Professor and Director of the Institute of Electrical Engineering and of the Integrated Systems Centre at EPF Lausanne, Switzerland. He is program leader of the program. Previously, he was Professor of Electrical Engineering at Stanford University.He holds a Nuclear Engineer degree (Politecnico di Milano, 1979), a M.S. and a Ph.D. degree in Electrical Engineering and Computer Science (University of California at Berkeley, 1980 and 1983).

Prof. De Micheli is a Fellow of ACM and IEEE, a member of the Academia Europaea and a Foreign Honorary member of the American Academy of Arts and Sciences. His research interests include several aspects of design technologies for integrated circuits and systems, such as synthesis for emerging technologies, networks on chips and 3D integration. He is also interested in heterogeneous platform design including electrical components and biosensors, as well as in data processing of biomedical information. He is author of: Synthesis and Optimization of Digital Circuits, McGraw-Hill, 1994, co-author and/or co-editor of eight other books and of over 750 technical articles. His citation h-index is 93 according to Google Scholar. He is member of the Scientific Advisory Board of IMEC (Leuven, B), CfAED (Dresden, D) and STMicroelectronics.

Prof. De Micheli is the recipient of the 2016 IEEE/CS Harry Goode award for seminal contributions to design and design tools of Networks on Chips, the 2016 EDAA Lifetime Achievement Award, the 2012 IEEE/CAS Mac Van Valkenburg award for contributions to theory, practice and experimentation in design methods and tools and the 2003 IEEE Emanuel Piore Award for contributions to computer-aided synthesis of digital systems. He received also the Golden Jubilee Medal for outstanding contributions to the IEEE CAS Society in 2000, the D. Pederson Award for the best paper on the IEEE Transactions on CAD/ICAS in 1987, and several Best Paper Awards, including DAC (1983 and 1993), DATE (2005), Nanoarch (2010 and 2012) and Mobihealth(2016).

He has been serving IEEE in several capacities, namely: Division 1 Director (2008-9), co-founder and President Elect of the IEEE Council on EDA (2005-7), President of the IEEE CAS Society (2003), Editor in Chief of the IEEE Transactions on CAD/ICAS (1997-2001). He has been Chair of several conferences, including Memocode (2014) DATE (2010), pHealth (2006), VLSI SOC (2006), DAC (2000) and ICCD (1989).