E. Tena-Sánchez, J. Castro, A. J. Acosta, “A methodology for optimized design of secure logic gates for DPA resistant circuits”, IEEE Journal on Emerging and Selected Topics on Circuits and Systems, Vol. 4, No. 2, pp. 203-215, June 2014.
J. M. Mora-Gutiérrez, C.J. Jiménez-Fernández and M. Valencia-Barrero. "Trivium hardware implementations for power reduction". International Journal of Circuit Theory and Applications. Published online in Wiley Online Library (wileyonlinelibrary.com) Nov. 2016. DOI: 10.1002/cta.2281
E. Tena-Sanchez, J. Castro, A. J. Acosta, "Low-Power Differential Logic Gates for DPA Resistant Circuits", 17th Euromicro Conference on Digital System Design (DSD'14), pp.671,674, 27-29 Aug. 2014. (Poster con proceso de selección por pares, presentado en Verona-Italia).
E. Tena-Sánchez, J. Castro, A. J. Acosta, "Design and test of a low power 90nm XOR/XNOR gate for cryptographic applications", 24th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS'14), pp.1,8, Sept. 29-Oct. 1, 2014. (Presentación oral con proceso de selección por pares, presentado en Palma de Mallorca-España).
E. Tena-Sánchez, A. J. Acosta, "DPA vulnerability analysis on Trivium stream cipher using an optimized power model", International Symposium on Circuits and Systems (ISCAS'15), pp. 1846-1849, May 2015. (Presentación oral con proceso de selección por pares, presentado en Lisboa-Portugal).
E. Tena-Sánchez, A. J. Acosta, "Optimized DPA attack on Trivium stream cipher using correlation shape distinguishers”, XXX Conference on Design of Circuits and Integrated Systems (DCIS'15), Nov. 2015. (Presentación oral con proceso de selección por pares, a presentar en Cascais-Portugal).
A.J. Acosta, “Low Power and Security Trade-off in Hardware: From True Random Number Generators to DPA Resilience”, Energy Secure Systems Architecture Workshop (ESSA’14), June 2014. (Ponencia oral invitada en congreso ISCA 2014, Minneapolis-USA).
J. M. Mora, C. J. Jiménez, E. Potestad, M. Valencia, “Low power implementation of Trivium stream cipher”, 17th Workshop on Cryptographic Hardware and Embedded Systems (CHES’15), 13-16 Sept. 2015. (Poster con proceso de selección directa, a presentar en Saint Malo-Francia).
E. Tena-Sanchez, A. J. Acosta, "Design and Characterization of Cryptohardware for ASIC-embedded Secure Applications to Prevent Power Analysis Attacks", 17th Workshop on Cryptographic Hardware and Embedded Systems (CHES'15), 13-16 Sept. 2015. (Poster con proceso de selección directa, a presentar en Saint Malo-Francia).
C.J. Jiménez, C. Baena, M. Valencia, J.M. Fernandez, A. Moreno, “A message transmission system with lightweight encryption as a project in a Master subject”, XI Congreso de Tecnologías, Aprendizaje y Enseñanza de la Electrónica, TAEE 2014. DOI: 10.1109/TAEE.2014.6900161 Accesible en IEEEXplore.
F.E. Potestad-Ordóñez, C.J. Jiménez-Fernández, M. Valencia-Barrero, ”Fault Attack on FPGA implementations of Trivium Stream Cipher”, International Symposium on Circuits and Systems (ISCAS’16), pp. 562-565, 2016.
F.E. Potestad-Ordóñez, C.J. Jiménez-Fernández, M. Valencia-Barrero, “Experimental and Timing Analysis Comparison of FPGA Trivium Implementations and their Vulnerability to Clock Fault Injection”, Design of Circuits and Integrated Systems (DCIS’16), 2016.
F.E. Potestad-Ordóñez, C.J. Jiménez-Fernández, M. Valencia-Barrero, "Fault Injection on FPGA implementations of Trivium Stream Cipher using Clock Attacks", Workshop on Trustworthy Manufacturing and Utilization of Secure Devices (TRUDEVICE'16), 2016.
Tena-Sánchez, E.; Acosta, A.J. and Nuñez J., "Secure Cryptographic Hardware Implementation Issues for High-Performance Applications”, Int. Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS’16), 2016.
Canas S., Tena-Sánchez, E. and Acosta, A.J., "A low-cost FPGA-based platform to perform fast Power/Electromagnetic Attacks on cryptographic circuits", Conf. on Design of Circuits and Integrated Systems (DCIS’16), 2016.
Tena-Sánchez, E, I. Durán, Canas S., and Acosta, A.J., "Vulnerability Evaluation and Secure Design Methodology of Cryptohardware for ASIC-embedded Secure Applications to Prevent Side-Channel Attacks", Workshop on Trustworthy Manufacturing and Utilization of Secure Devices (TRUDEVICE'16), 2016.
P. Brox, M. C. Martínez, E. Tena-Sánchez, I. Baturone, A. J. Acosta, “ASIC Solution for MIMO Piecewise-Affine Functions”, International Journal on Circuit Theory and Applications (aceptado para su publicación) DOI: 10.1002/cta.2058.
Javier Paredes Moreno. “Transmisión cifrada de información con un sensor de temperatura usando un protocolo I2C”. Trabajo fin de Grado, Grado en Ingeniería Electrónica Industrial (Univ. de Sevilla). Tutor: Carlos J. Jiménez Fernández. 2015.
Juan Carlos del Río Ruger. “Transmisión cifrada de información con un convertidor AD comercial mediante un protocolo SPI”. Trabajo fin de Grado, Grado en Ingeniería Electrónica Industrial (Univ. de Sevilla). Tutor: Carlos J. Jiménez Fernández. 2015.
Irene Durán Menor de Gaspar. “Análisis de la seguridad en dispositivos criptográficos frente a ataques laterales”. Trabajo Fin de Grado, Grado en Física (Univ. de Sevilla).
Tutor: Antonio J. Acosta. 2015.