TUTORIAL

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Leakage Aware Design of Nanometric CMOS Circuits

Leakage power is becoming a significant part of the global IC power budget requiring novel circuit design solutions in addition to innovation in technology leakage control techniques. The tutorial will strongly focus on leakage aware design techniques and the technological possibilities to reduce leakage. In addition, the state of the art and future research directions on leakage control from the technology to design techniques at different levels of abstraction will be presented.

Date and Location

The tutorial will take place on Tuesday, November 20, 2007 at Hotel Meliá Sevilla in Spain in conjunction with the XXII Conference on Design of Circuits and Integrated Systems.

Hotel Meliá Sevilla
Dr. Pedro de Castro, 1  
E-41004 Seville
SPAIN

Duration:
From 11:00 to 18:00

Program

TIME

TITLE

SPEAKER

10:00

Registration

 

11:00

Welcome

J. Figueras, UPC, Barcelona

11:15

Introduction, State of the art and Roadmap

Roberto Zafalon, ST Microelectronics Italy, CLEAN coordinator

12:00 Techniques to control leakage power at technology and device level E. Beigne, LETI, Grenoble,  France

13:00

Lunch

 

14:15

Techniques to control Leakage at Circuit and logic levels

J. Figueras, UPC, Barcelona

15:00 Leakage control for memory circuits Roberto Zafalon, ST Microelectronics, Italy

15:45

Coffee break

 

16:00 Adaptive Architectural Leakage Control Techniques Joan Figueras, UPC Barcelona

16:45

Power Aware IC Design

E. Beigne, LETI, Grenoble,  France

17:30

Q&A and general discussion

All participants

18:00

Closing

 


Description:

Introduction, State of the art and Roadmap

Roberto Zafalon, ST Microelectronics, Italy

The International Technology Roadmap for Semiconductors (ITRS) emphasizes the problems ahead related to an excessive increase of the power consumption of CMOS devices. The power budget may become the limiting factor to the development of high speed, high density IC’s which enable the new services and applications driving the ICT market.
With 65 nm and 45 nm nanometer CMOS the power consumption will be dominated by sub-threshold and gate leakage currents. Some technology (e.g., high-k dielectrics), circuit and architectural techniques can effectively control leakage power.

Techniques to control leakage power at technology and device level

Edith Beigne, LETI, France

As technology is scaled, circuits have to be more and more power effective either in terms of dynamic power or in terms of leakage. This presentation will deal with the technological possibilities to reduce leakage. That means presenting different devices architectures, taking into account variability and processes maturity. As technology cannot do all the job, the second part of the talk is focusing on design techniques to reduce leakage power and dynamic power considering SoC implementation. We will first focus on state of the art, explaining existing techniques at design level either "full custom" or tools driven


Techniques to control Leakage at Circuit and Logic levels

Joan Figueras, UPC, Spain

Circuit techniques to estimate and control power consumption will be presented considering switching and leakage power in present and future CMOS technologies.  Leakage control techniques based on multi- threshold, “Voltage Hopping”, Sleep Transistor Insertion (STI) with the required anchor circuits and input state assignment will be analyzed. Finally state of the art and future possibilities of leakage control will be explored.


Leakage control for memory circuits

Roberto Zafalon, ST Microelectronics, Italy

As larger fractions of the die area get dedicated to on chip memories, they have become one of the primary candidates for attacking the leakage problem.  The leakage power consumption is even more critical for memories than for any other component: their high density of integration translates into a high power density that increases temperature, which in turn affects leakage current exponentially. For this reasons, several leakage aware memory and cache structures, have been proposed. While most of these approaches tackle the leakage issues at the circuit level by careful design of individual memory cells, some other methods work at the micro-architectural level, typically using a partitioning-based paradigm.


Adaptive Architectural Leakage Control Techniques

Joan Figueras, UPC, Spain

As technology is scaled in the nanometric range the variability of the manufacturing process on the circuit parameters becomes critical. The classical "design margin" approach to compensate for uncertainty becomes ineffective and costly. An emerging design paradigm consists in the provision of "on-chip adaptivity" to compensate dynamically to variability. In this presentation the architectural trends to adaptively control leakage power will be explored. To reduce subthreshold leakage currents Adaptive Body Bias (ABB) has been used, however its efficiency for technologies with increasing tunneling currents becomes less efficient. Adaptive Supply Voltage (ASV) used to control active as well as leakage power will be presented. The combination of ASV and ABB permits to adapt the system to reduce power maintaining its highest frequency of operation.


Power Aware IC Design

Edith Beigne, LETI, France

As leakage power and total power is more and more an issue in deep submicron technologies, new design methodologies have to be explored in order to lower the total power consumption in complex SoC circuits. A circuit called ALPIN “Asynchronous Low Power Innovative NoC” has been designed in order to qualify different design techniques at reducing dynamic and static power consumption in a 65 nm CMOS technology. Different techniques as voltage scaling, VDD hopping and power switches insertion have been implemented on a complete GALS system. Physical implementation issue and use of standard CAD flows will also be addressed.

Speakers' profiles:

Roberto Zafalon Dr. Zafalon heads the Competence Centre for Low Power System Design of the Advanced System Technology group in STMicroelectronics, Agrate Brianza (Milano), Italy. Until 2000 he has been in charge of the Advanced Power and Timing team in Central R&D - Design Platform group, contributing to corporate CAD projects for innovative Design Solutions and methodologies in the field of timing verification and power-conscious design, high level power modelling, optimization and signal-integrity analysis, in order to achieve the full industrial exploitation of deep sub-micron technologies for complex System-on-Chip designs. As of today, he contributed to almost 60 international scientific publications so far, including conferences, Journals/Transactions and books. He holds 8 international patents, four European, three USA and one Japanese, in the field of low power design, processors and architectures. He is a fellow member of the STMicroelectronics Patent Committee. Dr. Zafalon gave invited full-day Tutorials talks on research topics related to “Low power design, architectures and methodologies” at many distinguished IEEE international conferences, including International Symposium on Circuits and Systems (ISCAS), Design Automation and Test in Europe (DATE), Design Automation Conference (DAC), International Conference on CAD (ICCAD) and Embedded Systems Conference (ESC). He is widely recognized by the research community in his field and he has been serving the technical committees of several IEEE conferences, including Design Automation Conference (DAC), Design Automation and Test in Europe (DATE, subcommittee’s chairman), Intl. Symposium on Low Power Electronics and Design (ISLPED) and Power And Timing Modeling Optimization and Simulation (PATMOS). He is an invited reviewer of IEEE Transaction on CAD, Transaction on VLSI, IEE Proceedings and serves as Subject Area Editor with Journal of System Architecture (Elsevier publisher). 

Edith Beigné received the Electronic Engineering Diploma from the National Polytechnic Institute of Grenoble, France, in 1998.
In 1998, she joined the CEA-LETI laboratory in the Center for Innovation in micro & nanotechnology (MINATEC), Grenoble. She was first involved in contacless RFID mixed signal systems. In 2001, she began the asynchronous logic design activity in cryptographic and contacless systems. Around the development of the FAUST project, she has designed a part of the asynchronous Network-On-Chip. Since 2006, she is in charge of ALPIN, a power aware GALS SoC implementing dynamic and static low power techniques based on an asynchronous NoC.

Joan Figueras obtained his Engineering Degree at the ETSEIB of the Universitat Politècnica de Catalunya and his MsC and PhD degrees from the University of Michigan in Ann Arbor. Currently, he works at the Engineering Dpt. of the UPC with research and teaching responsibilities in the area of Electronics, Digital and Mixed-Signal Design and Test. His research interests are centered in emerging topics in low power design and advanced test of electronic circuits and systems. He has an extensive publication record and has presented seminars and tutorials in professional meetings, NATO seminars on topics related to "Low Power Design" and "Quality in Electronics". He is currently vice-chair of the IEEE Test Technology Technical Council, editor of JETTA, and member of steering and program committees of several Test and Low Power Design Conferences.

Organization:    
The tutorial is organized by:    
  • UNIVERSITAT POLITECNICA DE CATALUNYA (UPC)
   
Prof. Joan Figueras   
(e-mail: figueras@eel.upc.edu)  
  • CSIC-IMSE-CNM
   
Prof. Francisco V. Fernández 
(e-mail: Francisco.Fernandez@imse.cnm.es)  
Prof. Jose M. de la Rosa    
(e-mail: jrosa@imse.cnm.es)  
Dr. Rafael Castro López   
(e-mail: castro@imse.cnm.es)  

Registration


Registration is necessary for all participants.

     

Industry

EUR 400,-*

Academia

EUR 200,-*

DCIS delegates

EUR 100,-*

Students

EUR 100,-*

  * All prices include taxes

Included with a registration are:

  • lunch
  • coffee breaks
  • printed slides binder
Registration deadline is November 6, 2007. Registrations after that deadline are subject to availability and will be charged with an additional fee of EUR 25,- (including taxes).