Call for papers
ETS09 Registration for tutorial is now open
|Monday, May, 25, 2009||9:00 – 13:00 and 14:30 – 17:30|
Tutorial 1: Advanced Topics and Recent Advances in Silicon Debug and Diagnosis
Srikanth VENKATARAMAN, Intel Corporation, USA; Miron ABRAMOVICI, DAFCA, Inc., USA; Robert AITKEN, ARM, USA.
The increasing design complexity along with the emergence of new failure mechanisms in the nanometer regime has significantly increased the complexity of verification, validation and manufacturing ramp of ICs. When pre‐silicon verification and validation uncovers design bugs, the process of diagnosing and debugging these issues is called design error diagnosis. From the time a new chip comes back from the fab until high‐volume production can start, the chip goes through functional silicon validation and debug to make sure it is free of design errors, and defect diagnosis and failure analysis to solve yield problems. These activities, referred to as silicon debug and diagnosis, have become the most time‐consuming phase in the development cycle of a new design, increasing to about 33% of the total time. This is a consequence of the increasing design complexity, along with the emergence of new failure mechanisms in nanometer technologies. Long time‐to‐volume and low manufacturing yield have a great detrimental impact on the economic viability and the overall success of a product. This tutorial covers the state of the art and the full spectrum of topics in silicon validation and debug and defect diagnosis ranging from the basic concepts to advanced applications and new DFD techniques. We will also describe successful debug and diagnosis methods used in real industrial products, industrial experiences, and case studies. Finally we will discuss future directions and challenges.