Call for papers
Workshop Technical Program
9:00-9:20: Opening Session
Keynote 1:
Mark KASSAB, Mentor Graphics, USA
Title: Are you using the right low-power test methodology?Abstract: Power has become one of the main concerns on the minds of test engineers. Excessive power consumption during capture increasingly compromises the value of at-speed test, and consequently a product's profit margins. Static power management methods introduce new challenges to achieving high quality goals. Several options with different trade-offs exist to deal with those challenges. As will be discussed, choosing the right methodology requires understanding what problems are being addressed, what is being tested, and what power conditions are required.
10:10 - 10:30: Coffe Break
Regular Papers:
Stephan Eggersglüß, Daniel Tille, Rolf Drechsler
A Two-Stage SAT-based ATPG Approach with Reduced Switching ActivityRené Kothe
Simultaneous Reduction of Test Data and Switching Activity for Transition Delay Tests
Embedded Tutorial 1:
Ilia POLIAN, University of Freiburg, Germany
Test of power supply noise -- causes, effects and testing
13:00 - 14:30: Lunch
Keynote 2:
Rob AITKEN, ARM, USA
Defects and Margins in Low Voltage MemoriesAbstract: The distinction between defects and parametric variation in nanometer designs is becoming difficult to quantify in nanometer technologies. Low voltage operation adds another layer of complexity to the subject. Specific examples are given for SRAM operation. The implications of these on other circuits of interest are discussed.
F.Wu, L.Dilillo, P.Girard, S.Pravossoudovitch, A.Virazel, A.Bosio, X.Wen
Trade-off between Power Dissipation and Delay Fault Coverage For LOS and LOC Testing Schemes
Irith Pomeranz, Sudhakar M. Reddy
Test Sequences with Reduced and Increased Switching ActivityJ. Freijedo, L.Costas, J. Semião, J.J. Rodríguez-Andina, M.J.Moure, F.Vargas, I.C.Teixeira, J.P.Teixeira
Delay Modeling for Power Noise-Aware Design and Test in 65nm FPGAs
16:30 - 16:50: Coffe Break
Embedded Tutorial 2:
Xiaoqing WEN, Kyushu Institute of Technology, Japan
Effects of IR-drop on VLSI testing and the impact on test generation and parametric test
Keynote 3:
Hans MANHAEVE, Q-Star Test nv, Belgium
Low-power and the future of IDDQ testing