Authors: P. Pouyan, E. Amat, A. Rubio, IEEE/ACM International Symposium on Nanoscale Architectures NANOARCH 2015, Boston, July 2015.
Author: Antonio Rubio Sola
Analysis and Design of an Adaptive Proactive Reconfiguration Approach for Memristive Crossbar Memories
Authors: P. Pouyan, E. Amat. A. Rubio, IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH’15, Boston, July 2015.
Degradation Stochastic Resonance Concept: Benefits of Controlled Noise Injection in Adaptive cell-based Architectures
Authors: N. Aymerich, S. Cotofana, A. Rubio, 7th International Conference on Unsolved Problems on Noise, Barcelona 2015.
Statistical Lifetime Analysis of Memristive Crossbar Matrix
Authors: P. Pouyan, E. Amat, A. Rubio, International Conference on Design and Technology of Integrated Systems in nanoscale Era (DTIS), Napols, Italy, April 2015.
Characterization of random telegraph noise and its impact on reliability of SRAM sense amplifiers
J. Martin-Martínez et al, “Characterization of random telegraph noise and its impact on reliability of SRAM sense amplifiers”, W07 Designing with Uncertainty, Opportunities and Challenges Workshop, Design, Automation & Test in Europe 2015. Grenoble.
Open access: http://hdl.handle.net/2117/27058
Statistical lifetime analysis in memristive crossbar
P. Pouyan, E. Amat and A. Rubio “Statistical lifetime analysis in memristive crossbar”, W07 Designing with Uncertainty, Opportunities and Challenges Workshop, Design, Automation & Test in Europe 2015. Grenoble.
Open access: not yet available
SET and noise fault tolerant circuit design techniques: Application to 7 nm FinFET
A. Calomarde, E. Amat, F. Moll, J. Vigara, A. Rubio, “SET and noise fault tolerant circuit design techniques: Application to 7 nm FinFET” Microelectronics and Reliability, Volume 54, Issue 4, April 2014, Pages 738–745.
Work published in January 2014 related with the objectives of the project but not supported economically by Maragda.
Open access link: http://hdl.handle.net/2117/23028
Feasibility of the embedded DRAM cells implementation withFinFET devices
Amat, E., Calomarde, A., Moll, F., Canal, R. and Rubio, A.,”Feasibility of embedded DRAM cells on FinFET technology”, IEEE Tr. on Computers, December 2014, DOI:10.1109/TC.2014.2375204
Open Access Link: http://upcommons.upc.edu/e-prints/urlFiles?idDrac=15451919
Impact of Adaptive Proactive Reconfiguration Technique on Vmin and Lifetime of SRAM Caches
Pouyan, P., Amat, E., Barajas, E. and Rubio, A.,”Impact of Adaptive Proactive Reconfiguration Technique on Vmin and Lifetime of SRAM Caches”, 5th Int. Simp. on Quality Electronic Design (ISQED), 2014, DOI:http://dx.doi.org/10.1109/ISQED.2014.6783303.
Open Access Link: http://hdl.handle.net/2117/24778
Reliability Challenges in Design of Memristive Memories
Pouyan, P., Amat, E. and Rubio, A.,”Reliability Challenges in Design of Memristive Memories”, 5th European Workshop on CMOS Variability (VARI), 2014, DOI:http://dx.doi.org/10.1109/VARI.2014.6957074.
Open Access link: http://hdl.handle.net/2117/25636
Adaptive Proactive Reconfiguration: A Technique for Process Variability and Aging Aware SRAM Cache Design
Pouyan, P., Amat, E. and Rubio, A., “Adaptive Proactive Reconfiguration: A Technique for Process Variability and Aging Aware SRAM Cache Design”, IEEE Tr. on VLSI, October 2014, DOI:http://dx.doi.org/10.1109/TVLSI.2014.2355873.
Open Access link: http://hdl.handle.net/2117/25262