SET and noise fault tolerant circuit design techniques: Application to 7 nm FinFET

A. Calomarde, E. Amat, F. Moll, J. Vigara, A. Rubio, “SET and noise fault tolerant circuit design techniques: Application to 7 nm FinFET” Microelectronics and Reliability, Volume 54, Issue 4, April 2014, Pages 738–745.

Work published in January 2014 related with the objectives of the  project but not supported economically by Maragda.

Open access link: http://hdl.handle.net/2117/23028