Automated generation of optimal performance trade-offs of integrated inductors

R. González-Echevarría, R. Castro-López, E. Roca, F.V. Fernández, J. Sieiro, N. Vidal and J.M. López-Villegas, “Automated generation of optimal performance trade-offs of integrated inductors,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, pp. 1269-1273, Vol. 33, No. 8, Aug. 2014.

DOI 10.1109/TCAD.2014.2316092

Generation of surrogate models of Pareto-optimal performance trade-offs of planar inductors

M. Kotti, R. González-Echevarría, F.V. Fernández, E. Roca, J. Sieiro, R. Castro-López, M.Fakhfakh and J.M. López-Villegas, “Generation of surrogate models of Pareto-optimal performance trade-offs of planar inductors”, Analog Integrated Circuits and Signal Processing, Vol. 78, No. 1, pp. 87-97, Jan. 2014.

doi:10.1007/s10470-013-0230-8

Fully Analytical Characterization of the Series Inductance of Tapered Integrated Inductors

Fábio Passos, M. Helena Fino, Elisenda Roca Moreno, “Fully Analytical Characterization of the Series Inductance of Tapered Integrated Inductors”, International Journal of Electronics and Telecommunications, vol. 60 (1), pp: 73-77, 2014

DOI: 10.2478/eletel-2014-0007

Open Acess: http://www.degruyter.com/view/j/eletel.2014.60.issue-1/eletel-2014-0007/eletel-2014-0007.xml

SET and noise fault tolerant circuit design techniques: Application to 7 nm FinFET

A. Calomarde, E. Amat, F. Moll, J. Vigara, A. Rubio, “SET and noise fault tolerant circuit design techniques: Application to 7 nm FinFET” Microelectronics and Reliability, Volume 54, Issue 4, April 2014, Pages 738–745.

Work published in January 2014 related with the objectives of the  project but not supported economically by Maragda.

Open access link: http://hdl.handle.net/2117/23028