A. Unutulmaz, G. Dundar, F.V. Fernández, “Template coding with LDS and applications in EDA”, Analog Integrated Circuits and Signal Processing, Vol. 78, No. 1, pp. 137-151, Springer, Jan. 2014.
2014 Journals
Maximizing Lyapunov Exponents in a Chaotic Oscillator by Applying Differential Evolution
V.H. Carbajal Gómez, E. Tlelo-Cuautle, F.V. Fernández, L.G. de la Fraga and C. Sánchez-López, “Maximizing Lyapunov Exponents in a Chaotic Oscillator by Applying Differential Evolution”, Int. J. of Nonlinear Sciences and Numerical Simulation, Vol. 15, No. 1, pp. 11-18, De Gruyter, Jan. 2014.
Efficient Hybrid Continuous-Time/Discrete-Time Cascade Sigma-Delta Modulators for Wideband Applications
J.G. García-Sánchez and J.M. de la Rosa: “Efficient Hybrid Continuous-Time/Discrete-Time
Cascade Sigma-Delta Modulators for Wideband Applications.” Microelectronics Journal, vol. 45, pp.
1234-1246, October 2014.
DOI 10.1016/j.mejo.2013.10.017
Open Access: http://hdl.handle.net/10261/107830
Guest Editorial: Special Section on the 2013 IEEE Custom Integrated Circuits Conference (CICC 2013)
J.M. de la Rosa, J.W.M. Rogers and V. Chandra: “Guest Editorial: Special Section on the 2013 IEEE
Custom Integrated Circuits Conference (CICC 2013).” IEEE Trans. on Circuits and Systems – I:
Regular Papers, vol. 61, pp. 2217-2218, August 2014.
Automated generation of optimal performance trade-offs of integrated inductors
R. González-Echevarría, R. Castro-López, E. Roca, F.V. Fernández, J. Sieiro, N. Vidal and J.M. López-Villegas, “Automated generation of optimal performance trade-offs of integrated inductors,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, pp. 1269-1273, Vol. 33, No. 8, Aug. 2014.
LC-based Bandpass Continuous-Time Sigma-Delta Modulators with Widely Tunable Notch Frequency
G. Molina-Salgado, A. Morgado, G. Jovanovic-Dolecek and J.M. de la Rosa: “LC-based Bandpass Continuous-Time Sigma-Delta Modulators with Widely Tunable Notch Frequency.” IEEE Trans. on Circuits and Systems – I: Regular Papers, vol. 61, pp. 1442-1455, May 2014.
Generation of surrogate models of Pareto-optimal performance trade-offs of planar inductors
M. Kotti, R. González-Echevarría, F.V. Fernández, E. Roca, J. Sieiro, R. Castro-López, M.Fakhfakh and J.M. López-Villegas, “Generation of surrogate models of Pareto-optimal performance trade-offs of planar inductors”, Analog Integrated Circuits and Signal Processing, Vol. 78, No. 1, pp. 87-97, Jan. 2014.
doi:10.1007/s10470-013-0230-8
Introduction to the special issue on SMACD 2012
F.V. Fernández, E. Roca and R. Castro-López, “Introduction to the special issue on SMACD 2012”, Analog Integrated Circuits and Signal Processing, Vol. 78, No. 1, pp. 61-73, Springer, Jan. 2014.
Open Access: http://hdl.handle.net/10261/92901
Fully Analytical Characterization of the Series Inductance of Tapered Integrated Inductors
Fábio Passos, M. Helena Fino, Elisenda Roca Moreno, “Fully Analytical Characterization of the Series Inductance of Tapered Integrated Inductors”, International Journal of Electronics and Telecommunications, vol. 60 (1), pp: 73-77, 2014
Open Acess: http://www.degruyter.com/view/j/eletel.2014.60.issue-1/eletel-2014-0007/eletel-2014-0007.xml
SET and noise fault tolerant circuit design techniques: Application to 7 nm FinFET
A. Calomarde, E. Amat, F. Moll, J. Vigara, A. Rubio, “SET and noise fault tolerant circuit design techniques: Application to 7 nm FinFET” Microelectronics and Reliability, Volume 54, Issue 4, April 2014, Pages 738–745.
Work published in January 2014 related with the objectives of the project but not supported economically by Maragda.
Open access link: http://hdl.handle.net/2117/23028
Feasibility of the embedded DRAM cells implementation withFinFET devices
Amat, E., Calomarde, A., Moll, F., Canal, R. and Rubio, A.,”Feasibility of embedded DRAM cells on FinFET technology”, IEEE Tr. on Computers, December 2014, DOI:10.1109/TC.2014.2375204
Open Access Link: http://upcommons.upc.edu/e-prints/urlFiles?idDrac=15451919
Adaptive Proactive Reconfiguration: A Technique for Process Variability and Aging Aware SRAM Cache Design
Pouyan, P., Amat, E. and Rubio, A., “Adaptive Proactive Reconfiguration: A Technique for Process Variability and Aging Aware SRAM Cache Design”, IEEE Tr. on VLSI, October 2014, DOI:http://dx.doi.org/10.1109/TVLSI.2014.2355873.
Open Access link: http://hdl.handle.net/2117/25262