These are the objectives of the MARAGDA project:
- Statistical characterization and modeling of variability and aging in advanced CMOS devices. With the introduction of new materials and device architectures, new aging mechanisms appear or those previously identified become even more harmful. In addition, the RAD paradigm requires a detailed and statistical knowledge of the variability/aging effects on the device performance. Consequently, the first objective of the project will be the statistical characterization (at the nanoscale and device levels) of the more relevant aging mechanisms in advanced FETs and their effects on device performance. Physics-based models for the time-dependent variability of devices will be proposed, to be implemented in circuit simulators.
- Unfolding of an efficient reliability-aware circuit simulation methodology. The real device aging must be evaluated in the particular context of the device within the circuit. Moreover, the device aging can have detrimental effects in the circuit performance. Therefore, the second objective of the project will be the development of an efficient statistical circuit simulation methodology that incorporates the time-dependent device variability, so that its effects can be evaluated at circuit level.
- Diagnosis of circuit performance degradation due to variability and aging. The third objective will be focused on the effects of device variability and/or aging on the circuit performance. They will be studied experimentally and through simulation (with the aid of the developed simulation tool) on some representative (digital and analog) circuit building blocks.
- Introduction of new design methodologies aimed at high-performance, low-power, (time-dependent) variability-resilient circuits. The fourth objective encompasses new design techniques and methodologies that deal with the negative impact of increasing device variability and aging and non-ideal scaling of device parasitics in circuit performance. These new design techniques aim at guaranteeing correct performance along the specified circuit lifetime while avoiding overdesign, i.e. highest performances with minimum fabrication cost and minimum power consumption. Three grand challenges envisioned in ITRS are addressed: “design productivity” (design cost remains the greatest threat to continuation of the semiconductor roadmap), “power management” and “reliability and resilience”.
- Development of reliability-aware reactive design strategies. The fifth objective complements the fourth one, by addressing innovative design strategies that force circuits to react to the effects of device variability and aging in the performance, yield and reliability of circuits. This clearly implies a key challenge to designers to be provided by new variability and aging aware design methodologies. These techniques, implemented in silicon, cause an overhead but also an improvement of performances and an enlargement of lifetime and manufacturing yield.
- Exploration of new circuit and system architectures for resistive switching technologies. In the fourth and fifth objectives, conventional circuit arquitectures are considered, which are conveniently modified to deal with the device variability/aging effects. However the emerging devices could open a new computing paradigm. The sixth objective of the project is oriented to the exploration of alternative disruptive solutions, in which the variability and aging of devices could be more effectively handled. In particular, the shape-shifting digital hardware concept (a reconfigurable and adaptive solution recently presented by the UAB and UPC groups), based on resistive-switching devices, will be investigated, as an alternative arquitecture for fault-tolerant systems.