Publications
2020
Journals
1. Ready-to-Fabricate RF Circuit Synthesis using a Layout- and Variability-Aware Optimization-based Methodology
F. Passos, E. Roca, R. Martins, N. Lourenço, S. Ahyoune, J. Sieiro, R. Castro-Lopez, N. Horta and F. V. Fernandez, IEEE Access, 2020.
DOI: 10.1109/ACCESS.2020.2980211
2. Design and analysis of secure emerging crypto-hardware using HyperFET devices
Ignacio María Delgado Lozano, Erica Tena-Sánchez, Juan Núñez, Antonio Acosta. IEEE Transactions on Emerging Topics in Computing. 2020.
DOI: 10.1109/TETC.2020.2977735
3. Projection of dual-rail DPA countermeasures in future FinFET and emerging TFET technologies
Ignacio María Delgado Lozano, Erica Tena-Sánchez, Juan Núñez, Antonio Acosta. Journal on Emerging Technologies in Computing Systems. 2020.
DOI:
4. Phase Transition Device for Phase Storing
M. J. Avedillo, J. M. Quintana, J. Núñez, IEEE Transactions on Nanotechnology, vol. 19, pp. 107-112, 2020.
DOI: 10.1109/TNANO.2020.2965243
5. A robust and automated methodology for the analysis of Time-Dependent Variability at transistor level
P. Saraza-Canflanca, J. Díaz-Fortuny, R. Castro-Lopez, E. Roca, J. Martin-Martinez, R. Rodriguez, M. Nafria, F.V. Fernández, Integration, vol. 72, pp. 13-20 (2020).
DOI: 10.1016/j.vlsi.2020.02.002
6. Flexible Setup for the Measurement of CMOS Time-Dependent Variability With Array-Based Integrated Circuits
J. Díaz-Fortuny, P. Saraza-Canflanca, R. Castro-Lopez, E. Roca, J. Martin-Martinez, R. Rodriguez, F.V. Fernández, M. Nafria, IEEE Trans. Instrumentation and Measurements, vol. 69, no. 3, pp. 853-864, March 2020.
7. A multilevel bottom-up optimization methodology for the automated synthesis of RF systems
F. Passos, E. Roca, J. Sieiro, R. Fiorelli, R. Castro-Lopez, J.M. López-Villegas, F. V. Fernandez IEEE Trans. on Computer Aided Design of Integrated Circuits and Systems, vol. 39(3), pp. 560-571, 2020.
DOI: 10.1109/TCAD.2018.2890528
8. Chaotic Image Encryption Using Hopfield and Hindmarsh–Rose Neurons Implemented on FPGA
E. Tlelo-Cuautle, J:D. Díaz-Muñoz, A.M. González-Zapata, R. Li, W.D. León-Salas, F.V. Fernández, O. Guillén-Fernández, I. Cruz-Vega. Sensors, vol. 20, 1326, 2020.
DOI: 10.3390/s20051326
International Conferences
1. Improving the reliability of SRAM-based PUFs in the presence of aging
P. Saraza-Canflanca, H. Carrasco-Lopez, P. Brox, R. Castro-Lopez, E. Roca and F.V. Fernandez, Proceedings IEEE 15th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2020.
DOI:
Books and Books Chapters
1. Modeling of variability and reliability in analog circuits
J. Martin-Martinez, J. Diaz-Fortuny, A. Toro-Frias, P. Martin-Lloret, P. Saraza-Canflanca, R. Castro-Lopez, R. Rodriguez, E. Roca, F.V. Fernandez, M. Nafria, chapter in Modelling Methodologies in Analogue Integrated Circuit Design, pp. 179-206, The Institution of Engineering and Technology, London (UK), 2020.
DOI:
2. On the usage of machine-learning techniques for the accurate modeling of integrated inductors for RF applications
F. Passos, E. Roca, R. Castro-Lopez, F.V. Fernandez, chapter in Modelling Methodologies in Analogue Integrated Circuit Design, pp. 155-178, The Institution of Engineering and Technology, London (UK), 2020.
DOI:
2019
Journals
1. A detailed study of the gate/drain voltage dependence of RTN in bulk pMOS transistors
P. Saraza-Canflanca, J. Martin-Martinez, R. Castro-Lopez, E. Roca, R. Rodriguez, M. Nafria, F.V. Fernandez, Microelectronic Engineering, vol. 215, 111004, 2019.
DOI: 10.1016/j.mee.2019.111004
2. A Smart Noise- and RTN-Removal Method for Parameter Extraction of CMOS Aging Compact Models
J. Diaz-Fortuny, J. Martin-Martinez, R. Rodriguez, R. Castro-Lopez, E. Roca, F.V. Fernandez, M. Nafria, Solid-State Electronics, vol. 159, pp. 99-105, 2019.
DOI: 10.1016/j.sse.2019.03.045
3. Two-Step RF IC Block Synthesis with Pre-Optimized Inductors and Full Layout Generation In-the-loop
R. Martins, N. Lourenço, F. Passos, R. Povoa, A. Canelas, E. Roca, R. Castro-López, J. Sieiro, F.V. Fernández, N. Horta, IEEE Trans. on COMPUTER-AIDED DESIGN of Integrated Circuits and Systems, vol. 38(6), pp.989-1002, 2019.
DOI: 10.1109/TCAD.2018.2834394
4. A two-step surrogate modeling strategy for single-objective and multi-objective optimization of radiofrequency circuits
F. Passos, R. González-Echevarría, E. Roca, R. Castro-López, F.V. Fernández, Soft Computing, vol. 23(13), PP.4911-4925, 2019.
DOI: 10.1007/s00500-018-3150-9
5. A Versatile CMOS Transistor Array IC for the Statistical Characterization of Time-Zero Variability, RTN, BTI and HCI
J. Diaz-Fortuny, J. Martin-Martinez, R. Rodriguez, R. Castro-Lopez, E. Roca, X. Aragonés, E. Baraja, D. Mateo, F.V. Fernandez and M. Nafria, IEEE Journal of Solid State Circuits, vol. 54(2), pp. 476-488, 2019.
DOI: 10.1109/JSSC.2018.2881923
6. Power and Speed Evaluation of Hyper-FET Circuits
J. Núñez, M.J. Avedillo, IEEE Access, vol. 7, pp 6724-6732, 2019.
DOI: 10.1109/ACCESS.2018.2889016
International Conferences
1. An IC Array for the Statistical Characterization of Time-Dependent Variability of Basic Circuit Blocks
P. Martin-Lloret, J. Nuñez, E. Roca, R. Castro-Lopez, J. Martin-Martinez, R. Rodriguez, M. Nafria, F.V. Fernandez. Proc. Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2019.
2. Synthesis of mm-Wave circuits using EM-simulated passive structure libraries
F. Passos, E. Roca, R. Castro-Lopez, N. Horta and F.V. Fernandez. Proc. Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2019.
3. Experimental Characterization of Time-Dependent Variability in Ring Oscillators
J. Nuñez, E. Roca, R. Castro-Lopez, J. Martin-Martinez, R. Rodriguez, M. Nafria and F.V. Fernandez. Proc. Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2019.
4. TiDeVa: A Toolbox for the Automated and Robust Analysis of Time-Dependent Variability at Transistor Level
P. Saraza-Canflanca, J. Diaz-Fortuny, R. Castro-Lopez, E. Roca, J. Martin-Martinez, R. Rodriguez, M. Nafria and F.V.Fernandez. Proc. Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2019.
5. Generation of Lifetime-Aware Pareto-Optimal Fronts Using a Stochastic Reliability Simulator
A. Toro-Frias, P. Saraza-Canflanca, F. Passos, P. Martin-Lloret, R. Castro-Lopez, E. Roca, J. Martin-Martinez, R. Rodriguez, M. Nafria and F.V. Fernandez. Proc. Design Automation and Test in Europe DATE 2019.
6. New method for the automated massive characterization of Bias Temperature Instability in CMOS transistors
P. Saraza-Canflanca, J. Diaz-Fortuny, R. Castro-Lopez, E. Roca, J. Martin-Martinez, R. Rodriguez, M. Nafria, F.V. Fernandez. Proc. Design Automation and Test in Europe DATE 2019.
7. A new time efficient methodology for the massive characterization of RTN in CMOS devices
G. Pedreira, J. Martin-Martinez, J. Diaz-Fortuny, P. Saraza-Canflanca, R. Rodriguez, R. Castro-Lopez, E. Roca, F.V. Fernandez and M. Nafria. Proc. IEEE International Reliability Physics Symposium IRPS 2019.
8. Device circuit co-design of HyperFET transistors
J. Núñez, M. Jiménez and M.J. Avedillo. Proc. Conference on Design of Circuits and Integrated Systems DCIS 2019.
9. Device Circuit Co-Design of HyperFET Transistors
J. Núñez and M.J. Avedillo. Proc. International Forum on Information Systems and Technologies INFOS 2019.
2018
Journals
1. A comparative analysis of VLSI trusted virtual sensors
M.C. Martínez-Rodríguez, P. Brox and I. Baturone, Microprocessors and Microsystems, vol. 61, pp 108-116, 2018.
DOI: 10.1016/j.micpro.2018.05.016
2. VLSI Design of Trusted Virtual Sensors
M.C. Martínez-Rodríguez, M.A. Prada-Delgado, P. Brox and I. Baturone, Sensors, vol. 18, no. 2, article 347, 2018.
DOI: 10.3390/s18020347
3. PVT-robust CMOS programmable chaotic oscillator: Synchronization of two 7-scroll attractors
V.H. Carbajal-Gomez, E. Tlelo-Cuautle, C. Sanchez-Lopez and F.V. Fernandez-Fernandez, Electronics, vol. 7, no. 10, article 252, 2018.
DOI: 10.3390/electronics7100252
4. A comparison of automated RF circuit design methodologies: online vs. offline passive component design
F. Passos, E. Roca, R. Castro-López and F.V. Fernández, IEEE Transactions on Very Large Scale Integration Systems, vol. 26, no. 11, pp 2386-2394, 2018.
DOI: 10.1109/TVLSI.2018.2859827
5. A novel design methodology for the mixed-domain optimization of a MEMS accelerometer
M. Pak, F.V. Fernandez and G. Dundar, Integration, vol. 62, pp 314-321, 2018.
DOI: 10.1016/j.vlsi.2018.03.018
6. Quasi-static PEEC planar solver using a weighted combination of 2D and 3D analytical Green's functions and a predictive meshing generator
S. Ahyoune, J. Sieiro, T. Carrasco, N. Vidal, J.M. López-Villegas, E. Roca and F.V. Fernández, Integration, vol. 63, pp 332-341, 2018.
DOI: 10.1016/j.vlsi.2018.02.006
7. Enhanced systematic design of a voltage controlled oscillator using a two-step optimization methodology
F. Passos, R. Martins, N. Lourenço, E. Roca, R. Póvoa, A. Canelas, R. Castro-López, N. Horta and F.V. Fernández, Integration, vol. 63, pp 351-361, 2018 .
DOI: 10.1016/j.vlsi.2018.02.005
8. Phase Transition FETs for Improved Dynamic Logic Gates
M.J. Avedillo, M. Jiménez and J. Núñez, IEEE Electron Device Letters, vol. 39, no. 11, pp 1776-1779, 2018 .
9. Impact of the RT-level architecture on the power performance of tunnel transistor circuits
M.J. Avedillo and J. Núñez, International Journal of Circuit Theory and Applications, vol. 46, no. 3, pp 647-655, 2018.
DOI: 10.1002/cta.2398
10. PVT-robust CMOS programmable chaotic oscillator: Synchronization of two 7-scroll attractors
V.H. Carbajal-Gomez, E. Tlelo-Cuautle, C. Sanchez-Lopez, F.V. Fernandez, Electronics, vol. 7, no. 10, 252, 2018.
DOI: 10.3390/electronics7100252
11. Guest Editorial Special Issue on Selected Papers from PRIME 2017 and SMACD 2017
G. Di Capua, N. Horta, F.V. Fernández, G. Dündar, S. Pennisi, G. Palumbo, M. Alioto, G. Giustoli, Integration, vol. 63, 273-274, 2018.
DOI: 10.1016/j.vlsi.2018.09.005
12. A novel design methodology for the mixed-domain optimization of a MEMS accelerometer
M. Pak, F.V. Fernández, G. Dündar, Integration, vol. 62, 314-321, 2018.
DOI: 10.1016/j.vlsi.2018.03.018
International Conferences
1. A Noise and RTN-Removal Smart Method for the Parameter Extraction of CMOS Aging Compact Models
J Diaz-Fortuny, J Martin-Martinez, R Rodriguez, R Castro-Lopez, E Roca, FV Fernandez, M Nafria. Proc. Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), 2018.
2. Weighted Time Lag Plot Defect Parameter Extraction and GPU-based BTI Modeling for BTI Variability
V.M. van Santen, J Diaz-Fortuny, H. Amrouch, J Martin-Martinez, R Rodriguez, R Castro-Lopez, E Roca, FV Fernandez, J. Henkel, M Nafria. Proc. IEEE International Reliability Physics Symposium (IRPS), 2018.
3. Automated massive RTN characterization using a transistor array chip
P. Saraza-Canflanca, J Diaz-Fortuny, A. Toro-Frias, R Castro-Lopez, E Roca, J Martin-Martinez, R Rodriguez, M Nafria, FV Fernandez. Proc. 15th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), pp. 29-32, 2018.
4. A Model Parameter Extraction Methodology Including Time-dependent Variability for Circuit Reliability Simulation
J. Diaz-Fortuny, P. Saraza-Canflanca, A. Toro-Frias, R. Castro-Lopez, J. Martin-Martinez, E. Roca, R. Rodriguez, F.V. Fernandez and M. Nafria. Proc. 15th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), pp. 53-56, 2018.
5. CMOS characterization and compact modelling for circuit reliability simulation
J. Diaz Fortuny, J. Martin-Martinez, R. Rodriguez, M. Nafria, R. Castro-Lopez, E. Roca and F.V. Fernandez. Proc. IEEE Int. Symposium on On-Line Testing and Robust System Design IOLTS 2018.
6. Analysis of Body Bias and RTN-induced Frequency Shift of Low Voltage Ring Oscillators in FDSOI Technology
E. Barajas, X. Aragones, D. Mateo, F. Moll, J. Martin-Martinez, R. Rodríguez, M. Portí, M. Nafria, R. Castro-López, E. Roca and F.V Fernández-Fernández. Proc. Int. Symposium on Power and Timing Modeling, Optimization and Simulation PATMOS 2018.
7. Handling the Effects of Variability and Layout Parasitics in the Automatic Synthesis of LNAs
F. Passos, R. Martins, N. Lourenço, E. Roca, R. Castro-López, R. Póvoa, A. Canelas, N. Horta and F.V. Fernández. Proc. 15 th Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2018.
8. Design considerations of an SRAM array for the statistical validation of time-dependent variability models
P. Saraza-Canflanca, D. Malagon, F. Passos, A. Toro, J. Nuñez, J. Diaz-Fortuny, R. Castro-Lopez, E. Roca, J. Martin-Martinez, R. Rodriguez, M. Nafria and F.V. Fernandez. Proc. 15th Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2018.
9. Lifetime Calculation Using a Stochastic Reliability Simulator for Analog ICs
A. Toro-Frías, P. Martín-Lloret, J. Martinez, R. Castro-Lopez, E. Roca, R. Rodriguez, M. Nafria and F.V. Fernandez. Proc. 15 th Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2018.
10. Benchmarking of nanometer technologies for DPA-resilient DPL-based cryptocircuits
E. Tena-Sánchez, I.M. Delgado-Lozano, J. Nuñez and A.J. Acosta. Proc. Conference on Design of Circuits and Integrated Systems DCIS 2018.
11. Inverting Versus Non-Inverting Dynamic Logic for Two-Phase Latch-free Nanopipelines
H.J. Quintero, M. Jimenez, M.J. Avedillo and J. Núñez. Proc. Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2018.
2017
Journals
1. Radio-Frequency Inductor Synthesis Using Evolutionary Computation and Gaussian-Process Surrogate Modeling
F. Passos, E. Roca, R. Castro-López, F.V. Fernández, Applied Soft Computing, vol. 60, pp 495-507, 2017.
DOI: 10.1016/j.asoc.2017.07.036
2. Parametric macromodeling of integrated inductors for RF circuit design
F. Passos, Y. Ye, D. Spina, E. Roca, R. Castro-López, T. Dhaene, F.V. Fernández, Microwave and Optical Technology Letters, vol. 59(5), pp 1207-1212, 2017.
DOI: 10.1002/mop.30498
3. An inductor modeling and optimization toolbox for RF circuit design
F. Passos, E. Roca, R. Castro-López, F.V. Fernández, Integration, vol. 58, pp 463-472, 2017.
DOI: 10.1016/j.vlsi.2017.01.009
4. An automated design methodology of RF circuits by using Pareto-optimal fronts of EM-simulated inductors
R. González-Echevarría, E. Roca, R. Castro-López, F.V: Fernández, J. Sieiro, J.M. López-Villegas y N. Vidal, IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 36(1), pp 15-26, 2017.
DOI: 10.1109/TCAD.2016.2564362
5. Insights into the Operation of Hyper-FET based Circuits
M.J. Avedillo, J. Núñez, IEEE Transactions on Electron Devices, vol. 64, no. 9, pp. 3912-3918, 2017.
6. Reducing the Impact of Reverse Currents in Tunnel FET Rectifiers for Energy Harvesting Applications
J. Núñez, M.J. Avedillo, IEEE Journal of Electron Devices Society, vol. 5, no. 6, pp. 530-534, 2017.
7. Model-based implementation of self-configurable intellectual property modules for image histogram calculation in FPGAs
L.M. Garcés-Socarrás, D.A. Romero, A.J. Cabrera, S. Sánchez-Solano and P. Brox, vol. 37, no. 2, pp 74-81, 2017.
DOI: 10.15446/ing.investig.v37n2.62328
International Conferences
1. A size-adaptive time-step algorithm for accurate simulation of aging in analog ICs
P Martín-Lloret, A Toro-Frías, J Martin-Martinez, R Castro-López, E Roca, R Rodriguez, M Nafria, FV Fernandez. Proc. IEEE Int. Symposium on Circuits and Systems (ISCAS), 2017.
2. A strategy to efficiently include electromagnetic simulations in optimization-based RF circuit design methodologies
F Passos, E Roca, R Castro-López, FV Fernández, J Sieiro, JM López-Villegas. Proc. IEEE MTT-S Int. Conference on Numerical Electromagnetic and Multiphysics Modeling and Optimization for RF, Microwave, and Terahertz Applications (NEMO), 2017.
3. An algorithm for a class of real-life multi-objective optimization problems with a sweeping objective
F Passos, E Roca, R Castro-López, FV Fernández. Proc. IEEE Congress on Evolutionary Computation (CEC), 2017.
4. Extending the frequency range of quasi-static electromagnetic solvers
S. Ahyoune, J. Sieiro, T. Carrasco, N. Vidal, J.M López-Villegas, E. Roca, F.V Fernández. Proc. 14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), 2017.
5. Including a stochastic model of aging in a reliability simulation flow
A Toro-Frías, P Martin-Lloret, R Castro-López, E Roca, FV Fernández, J Martin-Martinez, R Rodriguez, M Nafria. Proc. 14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), 2017.
6. Systematic design of a voltage controlled oscillator using a layout-aware approach
F Passos, E Roca, R Castro-López, FV Fernández, R Martins, N Lourenço, R Póvoa, A Canelas, N Horta. Proc. 14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), 2017.
7. TARS: A toolbox for statistical reliability modeling of CMOS devices
J Diaz-Fortuny, J Martin-Martinez, R Rodriguez, M Nafria, R Castro-Lopez, E Roca, FV Fernandez. Proc. 14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), 2017.
8. New mapping strategies for pre-optimized inductor sets in bottom-up RF IC sizing optimization
N Lourenço, R Martins, R Póvoa, A Canelas, N Horta, F Passos, R Castro-López, E Roca, FV Fernández. Proc. 14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), 2017.
9. Layout-aware challenges and a solution for the automatic synthesis of radio-frequency IC blocks
R Martins, N Lourenço, R Póvoa, A Canelas, N Horta, F Passos, R Castro-López, E Roca, FV Fernández. Proc. 14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), 2017.
10. CASE: A reliability simulation tool for analog ICs
P Martín-Lloret, A Toro-Frías, R Castro-López, E Roca, FV Fernández, J Martin-Martinez, R Rodriguez, M Nafria. Proc. 14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), 2017.
11. A transistor array chip for the statistical characterization of process variability, RTN and BTI/CHC aging
J Diaz-Fortuny, J Martin-Martinez, R Rodriguez, M Nafria, R Castro-Lopez, E Roca, FV Fernandez, E Barajas, X Aragones, D Mateo. Proc. 14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), 2017.
12. Statistical characterization of unreliability effects in a 65-nm CMOS transistor array
J Diaz-Fortuny, J Martin-Martinez, R Rodriguez, M Nafria, R Castro-Lopez, E Roca, FV Fernandez. Proc. 22nd International Mixed-Signal Testing Workshop (IMSTW), 2017.
13. Statistical characterization of reliability effects in nanometer CMOS using a versatile transistor array IC
J Diaz-Fortuny, J Martin-Martinez, R Rodriguez, M Nafria, R Castro-Lopez, E Roca, FV Fernandez, E Barajas, X Aragones, D Mateo. Proc. Design of Circuits and Integrated Systems Conference (DCIS), 2017.
14. Efficient Computation of Yield and Lifetime for Analog ICs under Process Variabiliy and Aging
A Toro-Frías, P Martin-Lloret, J Martin-Martinez, R Castro-Lopez, R Rodriguez, E Roca, M Nafria, FV Fernandez. Proc. Design of Circuits and Integrated Systems Conference (DCIS), 2017.
15. Design and characterization of a miniaturized implantable UHF RFID tag based on LTCC technology
A Garcia-Miquel, B Medina-Rodríguez, N Vidal, FM Ramos, E Roca, JM Lopez-Villegas. Proc. 11th European Conference on Antennas and Propagation (EUCAP), 2017.
16. Dependence of MOSFETs threshold voltage variability on channel dimensions
C Couso, J Diaz-Fortuny, J Martin-Martinez, M Porti, R Rodriguez, M Nafria, FV Fernandez, E Roca, R Castro-Lopez, E Barajas, D Mateo, X Aragones. Proc. Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), 2017.
17. Optimization of a MEMS accelerometer using a multiobjective evolutionary algorithm
M. Pak, F.V. Fernández, G. Dundar. Proc. 14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), 2017.
18. CMOS digital design of a trusted virtual sensor
M.C. Martínez-Rodríguez, M.A. Prada, P. Brox and I. Baturone. Proc. IEEE Nordic Circuits and Systems Conference (NORCAS), 2017.
19. Exploiting the variability of semiconductor fabrication process for hardware security
I. Baturone, P. Brox, R. Arjona and M.A. Prada-Delgado. How to survive in an unreliable world, IEEE CEDA Spain Chapter / NANOVAR Workshop, 2017.
2016
Journals
1. Reliability simulation for analog ICs: Goals, Solutions and Challenges
A Toro-Frías, P Martín-Lloret, J Martin-Martinez, R Castro-López, E Roca, R Rodriguez, M Nafria, FV Fernandez, Integration, vol. 55, pp 341-348, 2016.
DOI: 10.1016/j.vlsi.2016.05.002
2. Introduction to the special issue on Radio Frequency Integrated Circuits (RFIC) design techniques
E. Roca and J. Sieiro, Integration, vol. 52, pp 183-184, 2016.
DOI: 10.1016/j.vlsi.2015.11.001
3. Comparison of QMC-based yield-aware pareto front techniques for multi-objective robust analog synthesis
M. Pak, F.V. Fernández, G. Dundar. Integration, vol. 55, pp357-365, 2016.
DOI: 10.1016/j.vlsi.2016.04.004
4. Introduction to the special issue on SMACD 2015
G. Dundar, N. Horta, F.V. Fernandez, Integration, vol. 55, pp 293-294, 2016.
DOI: 10.1016/j.vlsi.2016.09.001
5. Design methodology for low-jitter differential clock recovery circuits in high performance ADCs
J. Núñez, A.J. Ginés, E. Peralías, A. Rueda, Analog Integrated Circuits and Signal Processing, vol. 89, no. 3, pp. 593-609, 2016.
DOI: 10.1007/s10470-016-0870-6
6. Comparative Analysis of Projected Tunnel and CMOS Transistors for Distinct Logic Applications Areas
J. Núñez, M.J. Avedillo, IEEE Transactions on Electron Devices, vol. 63, no. 12, pp. 5012-5020, 2016.
7. Comparison of TFETs and CMOS using optimal design points for power-speed trade-offs
J. Núñez, M.J. Avedillo, IEEE Transactions on Nanotechnology, vol. 16, no. 1, pp. 83-89, 2016.
8. Low-cost dedicated hardware IP modules for background subtraction in embedded vision systems
E. Calvo-Gallego, P. Brox and S. Sanchez-Solano, Journal of Real-Time Image Processing, vol. 12, no. 4, pp 681-695, 2016.
DOI: 10.1007/s11554-014-0455-5
9. Modificación automática de arquitecturas de módulos hardware de procesado de imágenes
L.M. Garcés-Socarrás, A.J. Cabrera-Sarmiento, S. Sánchez-Solano, P. Brox-Jiménez, E. Ieno and T. Cleber-Pimenta, Revista de Ingeniería Electrónica, Automática y Comunicaciones RIELAC, vol. 37, no. 3, pp 21-23, 2016.
International Conferences
1. Frequency-Dependent Parameterized Macromodeling of Integrated Inductors
F. Passos, E. Roca, R.Castro-López, F.V. Fernández, Y. Ye, D. Spina, T. Dhaene. Proc. International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), 2016.
2. SIDe-O: A Toolbox for Surrogate Inductor Design and Optimization
F. Passos, E. Roca, R.Castro-López, F.V. Fernández. Proc. International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), 2016.
3. Personal Exposure to Radiofrequency Electromagnetic Fields: University of Barcelona Study
N. Vidal, A. García-Miquel, A. Rios, J.M. López-Villegas, E Roca. Proc. European Conference on Antennas and Propagation (EUCAP), 2016.
4. Accurate Synthesis of Integrated RF Passive Components Using Surrogate Models
F. Passos, R. Gonzalez-Echevarria, E. Roca, R. Castro-Lopez, F.V. Fernandez. Proc. Design Automation and Test in Europe Conference and Exhibition (DATE), 2016.
5. DigitalLib: Una librería VHDL de bloques básicos para automatizar la construcción de sistemas digitales complejos
M. Brox, A. Gersnoviez, I. Bujalance, F.J. Quiles, M.A. Ortiz and P. Brox. Proc. Congreso de Tecnología, Aprendizaje y Enseñanza de la Electrónica (TAEE), 2016 .
6. Diseño de sistemas sensoriales basados en la plataforma Arduino
P. Brox, G. Huertas-Sanchez, A. Lopez-Angulo, M. Alvarez-Mora and I. Haya. Proc. Congreso de Tecnología, Aprendizaje y Enseñanza de la Electrónica (TAEE), 2016.
7. Hardware implementation of fuzzy inference systems for real-time video processing applications
S. Sánchez-Solano, M. Brox, E. Calvo-Gallego, A. Gersnoviez and P. Brox. Proc. XVIII Congreso Español sobre Tecnologías y Lógica Fuzzy (ESTYLF), 2016.
8. FPGA Implementation of the Two-Dimensional Fuzzy-ELA Algorithm for Image Enlargement
M. Brox, S. Sánchez-Solano, P. Brox, A. Gersnoviez and I. Baturone. Proc. XVIII Congreso Español sobre Tecnologías y Lógica Fuzzy (ESTYLF), 2016.
9. Complementary Tunnel Gate Topology to Reduce Crosstalk Effects
J. Núñez and M.J. Avedillo. Proc. Conference on Design of Circuits and Integrated Systems (DCIS), 2016.
10. Impact of Pipeline in the Power Performance of Tunnel Transistor Circuits
M.J. Avedillo and J. Núñez. Proc. Int. Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), 2016.
11. Secure Cryptographic Hardware Implementation Issues for High-Performance Applications
E. Tena-Sánchez, A.J. Acosta and J. Nuñez. Proc. Int. Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), 2016.
Books and Books Chapters
1. Circuit Realization of the Synchronization of Two Chaotic Oscillators with Optimized Maximum Lyapunov Exponen
V.H. Carbajal-Gómez, E. Tlelo-Cuautle, F.V. Fernández. Advances in Chaos Theory and Intelligent Control, vol. 337, pp 627-651, 2016.
DOI: 978-3-319-30340-6_26
2015
Journals
1. On the convex formulation of area for slicing floorplans
A. Unutulmaz, G. Dundar, F.V. Fernández. Integration, vol. 50, pp 74-80, 2015.
DOI: 10.1016/j.vlsi.2015.01.008
2. Improving speed of tunnel FETs logic circuits
M.J. Avedillo, J. Núñez. IET Electronics Letters, vol. 51, no. 21, pp 1702-1704, 2015.
DOI: 10.1049/el.2015.2416
3. Application specific integrated circuit solution for multi-input multi-output piecewise-affine functions
International Journal of Circuit Theory and Applications, vol. 44, no. 1, pp. 4-20, 2015.
DOI: 10.1002/cta.2058
4. Digital VLSI Implementation of Piecewise-Affine Controllers Based on Lattice Approach
IEEE Transactions on Control Systems Technology, vol. 23, no. 3, pp 842-854, 2015
DOI: 10.1109/TCST.2014.2345094
International Conferences
1. Transformation conditions of performance fronts of operational amplifiers
E Roca, R Castro-Lopez, M. Velasco, FV Fernandez. Proc. International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), 2015.
2. Surrogate modeling and optimization of inductor performances using Kriging functions
F. Passos, R Gonzalez-Echevarria, E Roca, R Castro-Lopez, FV Fernandez. Proc. International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), 2015.
3. A fast and accurate reliability simulation method for analog circuits
A.Toro-Frías, R. Castro-López, E. Roca, F.V. Fernández, J Martin-Martinez, R Rodriguez, M Nafria. Proc. International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), 2015.
4. Physical vs. Surrogate Models of Passive RF Devices
F. Passos, M. Kotti, R. González-Echevarría, M.H. Fino, M. Fakhfakh, E. Roca, R.Castro-López and F.V. Fernández. Proc. IEEE International Symposium on Circuits and Systems (ISCAS), 2015.
5. Design Space Exploration Using Hierarchical Composition of Performance Models
M. Velasco-Jiménez, R. Castro-López, E. Roca and F.V. Fernández. Proc. IEEE International Symposium on Circuits and Systems (ISCAS), 2015.
6. Integration of QMC based yield-aware pareto front techniques on MOEA/D for robust analog synthesis
M. Pak, G. Dundar, FV Fernandez. Proc. International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), 2015.
7. A two-step layout-in-the-loop design automation tool
G. Berkol, A. Unutulmaz, E. Afacan, G. Dündar, F.V. Fernandez, A.E. Pusane, F. Başkay. Proc. IEEE 13th International New Circuits and Systems Conference (NEWCAS), 2015.
8. Bloques de detección de matrículas sobre hardware reconfigurable
J.C. Gutiérrez, E. Augusto-Perdomo, L.M. Garcés-Socarrás, A.J. Cabrera Sarmiento, S. Sánchez-Solano and P. Brox-Jiménez. Proc. XVI Convención de Ingeniería Eléctrica (CIE), 2015.
9. Dedicated Hardware IP Module for Fingerprint Recognition
M.C. Martínez-Rodríguez, R. Arjona, P. Brox and I. Baturone. Proc. International Symposium on Consumer Electronics (ISCE), 2015.
10. Hardware implementation of a background substraction algorithm in FPGA-based platforms
E. Calvo-Gallego, P. Brox and S. Sánchez-Solano. Proc. IEEE International Conference on Industrial Technology (ICIT), 2015.
11. Programmable ASICs for Model Predictive Control
M.C. Martínez-Rodríguez, P. Brox, E. Tena, A.J. Acosta and I. Baturone. Proc. IEEE International Conference on Industrial Technology (ICIT), 2015.
12. Assessing application areas for tunnel transistor technologies
M.J. Avedillo and J. Núñez. Proc. Conference on Design of Circuits and Integrated Systems (DCIS), 2015.
13. Low-jitter differential clock driver circuits for high-performance high-resolution ADCs
J. Núñez, A.J. Gines, E. Peralías and A. Rueda. Proc. Conference on Design of Circuits and Integrated Systems (DCIS), 2015.
14. Improving robustness of dynamic logic based pipelines
H.J. Quintero, M.J. Avedillo and J. Núñez. Proc. Conference on Design of Circuits and Integrated Systems (DCIS), 2015.
15. An approach to the design of low-jitter differential clock recovery circuits for high performance ADCs
J. Núñez, A.J. Ginés, E.J. Peralías and A. Rueda. Proc. IEEE Latin American Symposium on Circuits and Systems (LASCAS), 2015.
Books and Books Chapters
1. Modeling of variability and reliability in analog circuits
E. Roca, R. Castro-López, F.V: Fernández, R. González-Echevarría, J. Sieiro, N. Vidal and J.M. López-Villegas, chapter in Computational Intelligence in Analog and Mixed-Signal (AMS) and Radio-Frequency (RF) Circuit Design, pp. 277-296, Springer International Publishing, Dordrecht (The Netherlands), 2015.
DOI: 10.1007/978-3-319-19872-9_10
2. Smas: A generalized and efficient framework for computationally expensive electronic design optimization problems
B. Liu, F.V. Fernández, G. Gielen, A. Karkar, A. Yakovlev, V. Grout, chapter in Computational Intelligence in Analog and Mixed-Signal (AMS) and Radio-Frequency (RF) Circuit Design, pp. 277-296, Springer International Publishing, Dordrecht (The Netherlands), 2015.
DOI: 10.1007/978-3-319-19872-9_9
3. Application of computational intelligence techniques to maximize unpredictability in multiscroll chaotic oscillators
VH Carbajal-Gómez, E Tlelo-Cuautle, FV Fernández, chapter in Computational Intelligence in Analog and Mixed-Signal (AMS) and Radio-Frequency (RF) Circuit Design, pp. 277-296, Springer International Publishing, Dordrecht (The Netherlands), 2015.
DOI: 10.1007/978-3-319-19872-9_3
