Bernabé Linares-Barranco, Personal Homepage.

http://www2.imse-cnm.csic.es/~bernabe

To IMSE home page

 For MATLAB Codes of ART1, ARTMAP, Fuzzy-ART and Fuzzy-ARTMAP   algorithms of the book "Adaptive Resonance Theory Microchips ",click here .
You can order the book from Kluwer   or from Amazon .

Links to MATLAB: http://www.mathworks.com http://www.mathtools.net

Link to the EU project CAVIAR web site: http://www.imse-cnm.csic.es/caviar

Link to citations in Google Scholar

Link to the IMSE Mismatch Page: click here .

Bernabé Linares-Barranco received the B. S. degree in electronic physics in June 1986 and the M. S. degree in microelectronics in September 1987, both from the University of Seville , Sevilla , Spain . From September 1988 until August 1991 he was a Graduate Student at the Dept. of Electrical Engineering of Texas A&M University. He received a first Ph.D. degree in high-frequency OTA-C oscillator design in June 1990 from the University of Seville, Spain, and a second Ph.D deegree in analog neural network design in December 1991 from Texas A&M University , College-Station, USA.

Since June 1991, he has been a Tenured Scientist at the National Microelectronics Center , (IMSE-CNM-CSIC ) Sevilla , Spain . From September 1996 to August 1997, he was on sabbatical stay at the Department of Electrical and Computer Engineering of the Johns Hopkins University . During Spring 2002 he was Visiting Associate Professor at the Electrical Engineering Department of Texas A&M University , College-Station, USA. In January 2003 he was promoted to Tenured Researcher, and in January 2004 to Full Professor.

He has been involved with circuit design for telecommunication circuits, VLSI emulators of biological neurons, VLSI neural based pattern recognition systems, hearing aids, precision circuit design for instrumentation equipment, bio-inspired VLSI vision processing systems, and VLSI transistor mismatch parameters characterization.

Dr. Linares-Barranco was corecipient of the 1997 IEEE Transactions on VLSI Systems Best Paper Award for the paper "A Real-Time Clustering Microchip Neural Engine", and of the 2000 IEEE Transactions on Circuits and Systems Darlington Award for the paper "A General Translinear Principle for Subthreshold MOS Transistors". He organized the 1995 Nips Post-Conference Workshop "Neural Hardware Engineering ". From July 1997 until June 1999 he has been Associate Editor of the IEEE Transactions on Circuits and Systems Part II , and from January 1998 until December 2009 he was also Associate Editor for IEEE Transactions on Neural Networks . Since April 2010 he is Associate Editor for the new journal "Frontiers in Neuromorphic Engineering", as part of the open access "Frontiers in Neuroscience" journal series (http://www.frontiersin.org/).

He is co-author of the book "Adaptive Resonance Theory Microchips ". He was Chief Guest Editor of the IEEE Transactions on Neural Networks   Special Issue on 'Hardware Neural Networks Implementations '. He is an IEEE Fellow since January 2010.

 
He was coordinator of the CAVIAR EU project.

Some video talks:

• Summary of AER sensing and processing (March 2009), <12 minutes .wmv> <25 minutes .wmv>

• Talk presented at “FET11: The European Future Technologies Conference and Exhibition”, Science Beyond Fiction, 4-6 May 2011, Budapest, Hungary. Talk title: “How to compute with memristors: dedicated bio-inspired architectures”. <22 minutes .avi>
  

Publications:

Books:

• T. Serrano-Gotarredona , B. Linares-Barranco and Andreas G. Andreou , Adaptive Resonance Theory Microchips, Kluwer Academic Publishers, 1998. ISBN: 0-7923-8231-5. (Table of Contents -PostScript 28K-) , (Preface - PostScript 58K-) , (Ordering Information) [To obtain the MATLAB codes of Appendix A (ART1, Fuzzy-ART, ARTMAP, Fuzzy-ARTMAP), click here ]

This book is also being promoted by `The MathWorks '.
See also book review by A. E. Hubbard and T. A. Hinck in Neural Networks, vol. 13, No. 4-5, pp. 555-556, 2000 (PDF 26K, 2 pages) .

Book Chapters:

• T. Serrano-Gotarredona, R. Serrano-Gotarredona and B. Linares-Barranco, "Log-Domain Circuit Techniques for Nonlinear Neural Networks with Complex Dynamics," Ch. 14 in Smart Adaptive Systems on Silicon, M. Valle (Ed.). Dordrecht: Kluwer Academic Publishers, pp. 229-251, 2004.

• T. Serrano-Gotarredona and B. Linares-Barranco, "Adaptive Resonance Theory Microchips," in Innovations in  ART Neural Networks: Design and Applications, L.C.Jain (Ed.), pp. 189-253, Physica Verlag (A Springer Verlag Company): Heidelberg, 2000.

• T. Serrano-Gotarredona and B. Linares-Barranco, "ART1 and ARTMAP VLSI Circuit Implementations," in Learning on Silicon. Adaptive VLSI Neural Systems, G. Cauwenberghs and M. Bayoumi (Eds.). Boston: Kluwer Academic Publishers, pp. 163-192, 1999. (Ordering Information)

• Bernabé Linares-Barranco and A. Rodríguez-Vázquez, "Harmonic Oscillators," in Encyclopedia of Electrical and Electronics Engineering , John G. Webster (Ed.), John  Wiley & Sons, Inc.  Vol. 8, pp. 632-642, 1999. (PDF 536K, 11 pages)

 

• Bernabé Linares-Barranco, E. Sánchez-Sinencio , A. Rodríguez-Vázquez, and J. L. Huertas, "CMOS Analog Neural Network Systems Based on Oscillatory Neurons", in Silicon Implementation of Pulse Coded Neural Networks, M. E. Zaghloul, J. Meador, and R. W. Newcomb (Eds.). Boston: Kluwer Academic Publishers, pp. 199-247, 1993.  ISBN: 0-7923-9449-6. (Ordering Information)

 Papers:

• Teresa Serrano-Gotarredona, T. Prodromakis, and B. Linares-Barranco, "A Proposal for Hybrid Memristor-CMOS Spiking Neuromorphic Learning Systems," IEEE Circuits and Systems Magazine, in Press.
• G. Indiveri, B. Linares-Barranco, R. Legenstein, G. Deligeorgis, and T. Prodromakis, "Integration of nanoscale memristor synapses in neuromorphic computing architectures," Nanotechnology, in Press.
• J. A. Pérez-Carrasco, B. Zhao, C. Serrano, B. Acha, T. Serrano-Gotarredona, S. Chen and B. Linares-Barranco, "Mapping from Frame-Driven to Frame-Free Event-Driven Vision Systems by Low-Rate Rate-Coding and Coincidence Processing. Application to Feed-Forward ConvNets," IEEE Trans. on Pattern Analysis and Machine Intelligence, in Press (author accepted pdf) (Video)
• T. Serrano-Gotarredona and B. Linares-Barranco, "A 128x128 1.5% Contrast Sensitivity 0.9% FPN 3us Latency 4mW Asynchronous Frame-Free Dynamic Vision Sensor Using Transimpedance Amplifiers," IEEE J. Solid-State Circuits, vol.48, No. 3, pp. 827-838, March 2013. (author accepted pdf) (ieeexplore)
• T. Serrano-Gotarredona, T. Masquelier, T. Prodromakis, G. Indiveri, and B. Linares-Barranco, "STDP and STDP Variations with Memristors for Spiking Neuromorphic Learning Systems," Frontiers in Neuromorphic Engineering, Front. Neurosci. 7:02. doi: 10.3389/fnins.2013.00002, 6 January 2013. (free open access link)
• C. Zamarreño-Ramos, R. Kulkarni, J. Silva-Martínez, T. Serrano-Gotarredona, and B. Linares-Barranco, "A 1.5ns OFF/ON Switching-Time Voltage-Mode LVDS Driver/Receiver Pair for Asynchronous AER Bit-Serial Chip Grid Links with up to 40 Times Event-Rate Dependent Power Savings," IEEE Trans. on Biomedical Circuits and Systems, in Press. (ieeexplore)
• C. Zamarreño-Ramos, A. Linares-Barranco, T. Serrano-Gotarredona, and B. Linares-Barranco, "Multi-Casting Mesh AER: A Scalable Assembly Approach for Reconfigurable Neuromorphic Structured AER Systems. Application to ConvNets," IEEE Trans. on Biomedical Circuits and Systems, vol. 7, No. 1, pp. 82-102, Feb. 2013. (ieeexplore)
• C. Zamarreño-Ramos, T. Serrano-Gotarredona, and B. Linares-Barranco, "A 0.35um Sub-ns Wake-up Time ON-OFF Switchable LVDS Driver-Receiver Chip I/O Pad Pair for Rate-Dependent Power Saving in AER Bit-Serial Links," IEEE Trans. on Biomedical Circuits and Systems, vol. 6, No. 5, pp. 486-497, October 2012. (ieeexplore)
• C. Farabet, R. Paz, J. Pérez-Carrasco, C. Zamarreño-Ramos, A. Linares-Barranco, Y. LeCun, E. Culurciello, T. Serrano-Gotarredona, and B. Linares-Barranco, "Comparison Between Frame-Constrained Fix-Pixel-Value and Frame-Free Spiking-Dynamic-Pixel ConvNets for Visual Processing," Frontiers in Neuromorphic Engineering, Front. Neurosci. 6:32. doi: 10.3389/fnins.2012.00032, 12 April 2012. (free open access link)
• L. Camuñas-Mesa, C. Zamarreño-Ramos, A. Linares-Barranco, A. Acosta-Jiménez, T. Serrano-Gotarredona, and B. Linares-Barranco, "An Event-Driven Multi-Kernel Convolution Processor Module for Event-Driven Vision Sensors," IEEE J. of Solid-State Circuits, vol. 47, No. 2, pp. 504-517, Feb. 2012. (ieexplore)
  
• S. Chen, P. Akselrod, B. Zhao, J. A. Pérez-Carrasco, B. Linares-Barranco and E. Culurciello, "Efficient feedforward categorization of objects and human postures with address-event image sensors," IEEE Trans. on Pattern Analysis and Machine Intelligence, vol. 34, No. 2, pp. 302-314, Feb. 2012. (ieeexplore)
• F. Alibart, S. Pleutin, O. Bichler, C. Gamrat, T. Serrano-Gotarredona, B. Linares-Barranco and D. Vuillaume, "A memristive nanoparticle/organic hybrid synapstor for neuro-inspired computing," Advanced Functional Materials, DOI: 10.1002/adfm.201101935, published online 13-Dec-2011.
• C. Zamarreño-Ramos, T. Serrano-Gotarredona, and B. Linares-Barranco, "An Instant-Startup Jitter-Tolerant Manchester-Encoding Serializer/Deserializar Scheme for Event-Driven Bit-Serial LVDS Inter-Chip AER Links," IEEE Trans. Circ. and Syst. Part-I, vol. 58, No. 11, pp. 2647-2660, Nov. 2011. (ieeexplore)
  
• J. A. Leñero-Bardallo, T. Serrano-Gotarredona, B. Linares-Barranco, "A 3.6us Asynchronous Frame-Free Event-Driven Dynamic-Vision-Sensor," IEEE J. of Solid-State Circuits, vol. 46, No. 6, pp. 1443-1455, June 2011. (ieeexplore)
• G. Indiveri, B. Linares-Barranco, T. J. Hamilton, A. van Schaik, R. Etienne-Cummings, T. Delbrück, S.-C. Liu, P. Dudek, P. Häfliger, S. Renaud, J. Schemmel, G. Cauwenberghs, J. Arthur, K. Hynna, F. Folowosele, S. Saïghi, T. Serrano-Gotarredona, J. Wijekoon, Y. Wang, K. Boahen, "Neuromorphic Silicon Neuron Circuits," Frontiers in Neuromorphic Engineering, Front. Neurosci. 5:73. doi: 10.3389/fnins.2011.00073, 31 May 2011. (free open access link)
• L. Camuñas-Mesa, A. Acosta-Jiménez, C. Zamarreño-Ramos, T. Serrano-Gotarredona, and B. Linares-Barranco, "A 32x32 Pixel Convolution Processor Chip for Address Event Vision Sensors with 155ns Event Latency and 20Meps Throughput," IEEE Trans. Circ. and Syst. Part-I, vol. 58, No. 4, pp. 777-790, April 2011. (ieeexplore)
• C. Zamarreño-Ramos, L. A. Camuñas-Mesa, Jose A. Perez-Carrasco, T. Masquelier, T. Serrano-Gotarredona, and B. Linares-Barranco, "On Spike-Timing-Dependent-Plasticity, Memristive Devices, and building a Self-Learning Visual Cortex," Frontiers in Neuromorphic Engineering, Front. Neurosci. 5:26, 2011. doi: 10.3389/fnins.2011.00026, 17 March 2011. (free open access link)
  
• J. A. Leñero-Bardallo, T. Serrano-Gotarredona, B. Linares-Barranco, "A 5-Decade Dynamic Range Ambient-Light-Independent Calibrated Signed-Spatial-Contrast AER Retina with 0.1ms Latency and Optional Time-to-First-Spike Mode," IEEE Trans. Circ. and Syst., Part-I, vol. 57, No. 10, pp. 2632-2643, October 2010. (ieeexplore)
  
• J. A. Pérez-Carrasco, B. Acha, C. Serrano, L. Camuñas-Mesa, T. Serrano-Gotarredona, and B. Linares-Barranco, "Fast Vision through Frame-less Event-based Sensing and Convolutional Processing. Application to Texture Recognition," IEEE Trans. Neural Networks, vol. 21, No. 4, pp. 609-620, April 2010. (ieeexplore)
  
• G. Vicente-Sanchez,  J. Velarde-Ramirez, T. Serrano-Gotarredona, and B. Linares-Barranco, "A Weak-to-Strong Inversion Mismatch Model for Analog Circuit Design," Int. Journal of  Analog Integrated Circuits and Signal Processing, 59, pp. 325-340, 2009.
• B. Linares-Barranco and T. Serrano-Gotarredona, “Memristance can explain Spike-Time-Dependent-Plasticity in Neural Synapses,” Available from Nature Precedings <http://hdl.handle.net/10101/npre.2009.3010.1> (2009)
• R. Serrano-Gotarredona, M. Oster, P. Lichtsteiner, A. Linares-Barranco, R. Paz-Vicente, F. Gómez-Rodríguez, L. Camuñas-Mesa, R. Berner, M. Rivas, T. Delbrück, S. C. Liu, R. Douglas, P. Häfliger, G. Jiménez-Moreno, A. Civit, T. Serrano-Gotarredona, A. Acosta-Jiménez, B. Linares-Barranco, "CAVIAR: A 45k-Neuron, 5M-Synapse, 12G-connects/sec AER Hardware Sensory-Processing-Learning-Actuating System for High Speed Visual Object Recognition and Tracking," IEEE Trans. on Neural Networks, vol. 20, No. 9, pp. 1417-1438, September 2009.  (ieeexplore)
• J. A. Leñero-Bardallo, T. Serrano-Gotarredona, and B. Linares-Barranco, "A Calibration Technique for Very Low Current and Compact Tunable Neuromorphic Cells. Application to 5-bit 20nA DACs," IEEE Trans. Circuits and Systems, Part-II: Brief Papers, vol. 55, No. 6, pp. 522-526, June 2008. (PDF 640K, 5 pages).
• R. Serrano-Gotarredona, T. Serrano-Gotarredona, A. Acosta-Jimenez, C. Serrano-Gotarredona, J. A. Perez-Carrasco, A. Linares-Barranco, G. Jimenez-Moreno, A. Civit-Ballcels, and B. Linares-Barranco, "On Real-Time AER 2D Convolutions Hardware for Neuromorphic Spike Based Cortical Processing," IEEE Trans. on Neural Networks, vol. 19, No. 7, pp. 1196-1219, July 2008. (PDF 7.7M, 24 pages).
• R. Serrano-Gotarredona, L. Camuñas-Mesa, T. Serrano-Gotarredona, J. A. Leñero-Bardallo, and B. Linares-Barranco, "The Stochastic I-Pot: A Circuit Block for Programming Bias Currents," IEEE Trans. Circuits and Systems, Part-II: Brief Papers, vol. 54, No. 9, pp. 760-764, September 2007. (PDF 252K, 5 pages).
• Bernabe Linares-Barranco and Teresa Serrano-Gotarredona,  "On an Efficient CAD Implementation of the Distance Term in Pelgrom's Mismatch Model," IEEE Trans. on CAD, vol. 26, No. 8, pp. 1534-1538, August 2007. (PDF 216K, 5 pages).
• J. Costas-Santos, T. Serrano-Gotarredona, R. Serrano-Gotarredona and B. Linares-Barranco, "A Spatial Contrast Retina with On-chip Calibration for Neuromorphic Spike-Based AER Vision Systems," IEEE Trans. Circuits and Systems, Part-I: Regular Papers, vol. 54, No. 7, pp. 1444-1458, July 2007. (PDF 1.6M, 15 pages).
• Alejandro Linares-Barranco, Matthias Oster, Daniel Cascado, Gabriel Jimenez, Anton Civit, Bernabe Linares-Barranco, "Inter-Spike-Intervals Analysis of AER Poisson like Generator Hardware," Neurocomputing, 70, pp. 2692-2700, May 2007. (PDF 224K, 13 pages)
• R. Serrano-Gotarredona, T. Serrano-Gotarredona, A. Acosta-Jimenez, and B. Linares-Barranco, "A Neuromorphic Cortical-Layer Microchip for Spike-Based Event Processing Vision Systems," IEEE Trans. Circuits and Systems, Part-I: Regular Papers, vol. 53, No. 12, pp. 2548-2566, December 2006. (PDF, 4.3M, 19 pages).
• Teresa Serrano-Gotarredona and Bernabé Linares-Barranco, "A Low-Power Current Mode Fuzzy-ART Cell," IEEE Trans. on Neural Networks, vol. 17, No. 6, pp. 1666-1673, November 2006. (PDF 501K, 8 pages).
• Alejandro Linares-Barranco, Gabriel Jimenez-Moreno, Bernabé Linares-Barranco and Antón Civit-Ballcels, "On Algorithmic Rate-Coded AER Generation," IEEE Transactions on Neural Networks, vol. 17, No. 3, pp. 771-788, May 2006. (PDF 973K, 18 pages)
• Bernabé Linares-Barranco, Teresa Serrano-Gotarredona , Juan Ramos-Martos, Joaquin Ceballos-Caceres, Jose Miguel Mora, and Alejandro Linares-Barranco, "A Precise 90º Quadrature OTA-C Oscillator Tunable in the 50-130 MHZ Range," IEEE Trans. on Circuits and Systems, Part I , vol. 51, No. 4, pp. 649-663, April 2004 (PDF 609K,15 pages) .
• Teresa Serrano-Gotarredona and Bernabé Linares-Barranco, "Log-Domain Implementation of Complex Dynamics Reaction-Diffusion Neural Networks," IEEE Trans. on Neural Networks , vol. 14, No. 5, pp. 1337-1355, September 2003 (PDF 3.90M, 19 pages) .
• Bernabé Linares-Barranco, Teresa Serrano-Gotarredona , and Rafael Serrano-Gotarredona, "Compact Low-Power Calibration Mini-DACs for Neural Massive Arrays with Programmable Weights," IEEE Trans. on Neural Networks, vol. 14, No. 5, pp. 1207-1216, September 2003 (PDF 1.28M, 10 pages) .
• Bernabé Linares-Barranco, Teresa Serrano-Gotarredona , Rafael Serrano-Gotarredona, and Clara Serrano-Gotarredona, "Current-Mode Techniques for Sub-Pico Ampere Circuit Design," Int. Journal of  Analog Integrated Circuits and Signal Processing, vol. 38, pp. 103-119, 2004. (PDF 417K, 17 pages)
• Bernabé Linares-Barranco and Teresa Serrano-Gotarredona , "On the Design and Characterization of Femtoampere Current-Mode Circuits," IEEE Journal of Solid-State Circuits, vol. 38, No. 8, pp. 1353-1363, August 2003. (PDF 797K, 10 pages) .
• Bernabé Linares-Barranco, Teresa Serrano-Gotarredona , J. Ramos-Martos, J. Ceballos-Caceres, J. M. Mora, and A. Linares-Barranco, "Precise 90º Quadrature Current-Controlled Oscillator Tunable between 50-130MHz," Electronics Letters, vol. 39, No. 11, pp. 823-825, 29th May 2003. (PDF 438K, 3 pages) .
• Teresa Serrano-Gotarredona and Bernabé Linares-Barranco, "Current mode fully programmable piece-wise linear block for neuro fuzzy applications," IEE Electronics Letters , vol. 38, No. 20, September 2002, pp. 1165-1166.  (PDF 310K, 2 pages) .
• Teresa Serrano-Gotarredona , Andreas G. Andreou , and Bernabé Linares-Barranco, "A Programmable VLSI Filter Architecture for Application in Real Time Vision Processing Systems," International Journal of Neural Systems, Special Issue on New Trends in Neural Network Implementations (invited), vol. 10, No. 3, pp. 179-190, June 2000. (PDF 585K, 12 pages)
• Teresa Serrano-Gotarredona and Bernabé Linares-Barranco, "A New 5-Parameter MOS Transistor Mismatch Model," IEEE Electron Device Letters, vol. 21, No. 1, pp. 37-39.January 2000. (PDF 144K, 3 pages)
• Teresa Serrano-Gotarredona and Bernabé Linares-Barranco, "Systematic Width-and-Length Dependent CMOS Transistor Mismatch Characterization and Simulation," Analog Integrated Circuits and Signal Processing, Kluwer Academic Publishers, vol. 21,  pp. 271-296, December 1999. (PDF 1.4M, 26 pages)
• Teresa Serrano-Gotarredona , Bernabé Linares-Barranco, and Andreas G. Andreou , "Very Wide Range Tunable CMOS/Bipolar Current Mirrors with Voltage Clamped Input," IEEE Trans. Circuits and Systems (Part I): Fundamental Theory and Applications, pp. 1398-1407, November 1999. (PDF 433K, 10 pages)
• Teresa Serrano-Gotarredona , Andreas G. Andreou , and Bernabé Linares-Barranco,  "AER Image Filtering Architecture for Vision Processing Systems," IEEE Trans. Circuits and Systems (Part I): Fundamental Theory and Applications, vol. 46, No. 9, pp. 1064-1071, September 1999. (PDF 287K, 8 pages) .
• Teresa Serrano-Gotarredona , Bernabé Linares-Barranco, and Andreas G. Andreou , "Bipolar/CMOS Current-Source Flip-Flop for Application in Neuro-Fuzzy Systems," Electronics Letters, vol. 35, No. 16, pp. 1326-1328, 5th August 1999. (PDF 223K, 3 pages) .
• Teresa Serrano-Gotarredona , Bernabé Linares-Barranco, and Andreas G. Andreou , "A General Translinear Principle for Subthreshold MOS Transistors," IEEE Trans. Circuits and Systems (Part I): Fundamental Theory and Applications , vol. 46, No. 5, pp. 607-616, May 1999. (PDF 335K, 10 pages) {This paper received the 2000 IEEE Trans. on Circuits and Systems Darlington Award}.
• Teresa Serrano-Gotarredona   and Bernabé Linares-Barranco, "7-Decade Tuning Range CMOS OTA-C Sinusoidal VCO", Electronics Letters, vol. 34, No. 17, pp. 1621-1622,  20th August 1998. (PDF 154K, 4 pages)
• Teresa Serrano-Gotarredona and Bernabé Linares-Barranco, "A High-Precision Current-Mode WTA-MAX Circuit with Multi-Chip Capability," IEEE Journal of Solid-State Circuits , vol. 33, no. 2, pp. 280-286, February 1998. (PDF 191K, 7 pages)
• Teresa Serrano-Gotarredona and Bernabé Linares-Barranco, "An ART1 Microchip and its use in Multi-ART1 Systems," IEEE Transactions on Neural Networks , vol. 8, No. 5, pp. 1184-1195, September 1997. (PDF 860K, 11 pages)
• Teresa Serrano-Gotarredona and Bernabé Linares-Barranco, "A Real-Time Clustering Microchip Neural Engine," IEEE Transactions on VLSI Systems, vol. 4, No. 2, pp. 195-209, June 1996. (PDF 2.2M, 16 pages)   {This paper received the 1997 IEEE Trans. on VLSI Systems Best Paper Award}. Its abstract has been included in: Serrano-Gotarredona, T and Linares-Barranco, B "A Real-Time Clustering Microchip Neural Engine," Abstracts on Microelectronics And Reliability (Elsevier Science), Vol: 37, Issue: 8, August 1997, pp. 1285.
• Teresa Serrano-Gotarredona and Bernabé Linares-Barranco, "A Modified ART1 Algorithm more suitable for VLSI Implementations," Neural Networks, vol. 9, No. 6, pp. 1025-1043, 1996. (PDF 1.3M, 19 pages)
• Teresa Serrano-Gotarredona and Bernabé Linares-Barranco, "A Modular Current-Mode High-Precision Winner-Take-All Circuit," IEEE Transactions on Circuits and Systems (Part II):Analog and Digital Signal Processing, vol. 42, No. 2, pp. 132-134, February 1995. (PDF 190K, 3 pages)
• Teresa Serrano-Gotarredona and Bernabé Linares-Barranco, "The Active-Input Regulated-Cascode Current Mirror," IEEE Transactions on Circuits and Systems (Part I): Fundamental Theory and Applications, vol. 41, No. 6, pp. 464-467, June 1994. (PDF 188K, 4 pages)
• Bernabé Linares-Barranco, Edgar Sánchez-Sinencio , Angel Rodríguez-Vázquez, And J. L. Huertas , "A CMOS Analog Adaptive BAM With On-chip Learning and Weight Refreshing," IEEE Transactions on Neural Networks, May 1993, Vol. 4, No. 3, Pp. 445-455. (PDF 866K,  11 pages)
• Bernabé Linares-Barranco, Angel Rodríguez-Vázquez, José L. Huertas, and Edgar Sánchez-Sinencio , "On the Generation Design and Tuning of OTA-C High Frequency Sinusoidal Oscillators", IEE Proceedings-Part G, Circuits Devices and Systems , vol. 139, No. 5, October 1992, pp. 557-568. (PDF 1.0M, 12 pages)
• Bernabé Linares-Barranco, Edgar Sánchez-Sinencio , Angel Rodríguez-Vázquez, and José L. Huertas, "A Modular T-Mode Design Approach for Analog Neural Network Hardware Implementations", IEEE Journal of Solid-State Circuits, vol. 27, No. 5, May 1992, pp. 701-713. (PDF 1.2M, 13 pages)
• Bernabé Linares-Barranco, Edgar Sánchez-Sinencio , Angel Rodríguez-Vázquez and José Luis Huertas, "A CMOS Implementation of FitzHugh-Nagumo Neuron Model", IEEE Journal of Solid-State Circuits, vol. 26, No. 7, pp. 956-965, July 1991. (PDF 1.2M, 10 pages)
• Bernabé Linares-Barranco, Angel Rodríguez-Vázquez, Edgar Sánchez-Sinencio and José Luis Huertas, "CMOS OTA-C High-Frequency Sinusoidal Oscillators", IEEE Journal of Solid-State Circuits, vol. 26, No. 2, pp. 160-165, February 1991. (PDF 635K, 6 pages)
• Angel Rodríguez-Vázquez, Bernabé Linares-Barranco, José Luis Huertas and Edgar Sánchez-Sinencio , "On the Design of Voltage Controlled Sinusoidal Oscillators using OTAs", IEEE Transactions on Cicuits and Systems, vol.37, No.2, pp. 198-211, February 1990. (PDF 1.1M, 14 pages). Corrections, vol. 38, no. 11, pp. 1405-1406, November 1991.(PDF)
• Edgar Sánchez-Sinencio , Jaime Ramírez-Angulo , Bernabé Linares-Barranco and Angel Rodríguez-Vázquez, "Operational Transconductance Amplifier-Based Nonlinear Function Syntheses", IEEE Journal of Solid-State Circuits, vol.24, No.6, pp. 1576-1586, December 1989. (PDF 1.1M, 11 pages)
• Bernabé Linares-Barranco, Edgar Sánchez-Sinencio , Angel Rodríguez-Vázquez and José Luis Huertas, "A 10 MHz Voltage-Controlled OTA Quadrature Oscillator", Electronics Letters , 8th June 1989, vol.25, No.12, pp. 765-767. (PDF 352K, 3 pages)
• Bernabé Linares-Barranco, Edgar Sánchez-Sinencio , Angel Rodríguez-Vázquez and José Luis Huertas, "A Programmable Neural Oscillator Cell", IEEE Transactions on Circuits and Systems, May 1989, CAS-36, No.5, pp. 756-761. (PDF 490K, 6 pages)

 

Some Relevant International Symposiums Papers (not updated):

• R. Serrano-Gotarredona, M. Oster, P. Lichtsteiner, A. Linares-Barranco, R. Paz- Vicente, F. Gómez-Rodríguez, H. Kolle Riis, T. Delbrück, S. C. Liu, S. Zahnd, A. M. Whatley, R. Douglas, P. Häfliger, G. Jimenez-Moreno, A. Civit, T. Serrano-Gotarredona, A. Acosta-Jiménez, B. Linares-Barranco, "AER Building Blocks for Multi-Layer Multi-Chip Neuromorphic Vision Systems," Advances in Neural Information Processing Systems 18, Y. Weiss and B. Scholkopf and J. Platt (Eds.), MIT Press, Cambridge, MA, 2006. (PDF 923K, 8 pages).
• L. Vancaillie, F. Silveira, B. Linares-Barranco, T. Serrano-Gotarredona, D. Flandre,  " MOSFET mismatch in weak/moderate inversion: model needs and implications for analog design",Proc. of the 2003 European Solid State Circuits Conference, (ESSCIRC'03), pp. 671-674, September 2003. (PDF 118K, 4 pages) .
• T. Serrano-Gotarredona and B. Linares-Barranco,  "CMOS Mismatch Model valid from Weak to Strong Inversion",Proc. of the 2003 European Solid State Circuits Conference, (ESSCIRC'03), pp. 627-630, September 2003. (PDF 2.98M, 4 pages).
• B. Linares-Barranco and T. Serrano-Gotarredona,  "Reliable Handling of Fempto-Ampere Currents in Standard CMOS," Proc. of the 2002 European Solid State Circuits Conference, (ESSCIRC'02), pp. 109-112, September 2002.
• T. Serrano-Gotarredona and B. Linares-Barranco, "A 5-Parameters Mismatch Model for Short Channel MOS Transistors," Proceedings of the 1999 European Solid State Circuits Conference (ESSCIRC99), pp. 440-443,1999. (PDF 266K, 4 pages) .
• T. Serrano-Gotarredona, B. Linares-Barranco and Andreas G. Andreou, "MOS/Bipolar active Input Current Mirrors with 13-Decades Gain Adjustment Range," Proceedings of the 1998 European Solid State Circuits Conference (ESSCIRC98), pp. 296-299, 1998. (PDF 142K, 4 pages) .

 

Patents:

• Teresa Serrano Gotarredona y Bernabe Linares Barranco, "Circuito para el reconocimiento y establecimiento de categorias de patrones binarios," spanish patent, registration number 9401031, publication number 2103176, 1994.

Theses and Dissertations:

• Bernabe Linares Barranco, "Quasi-Sinusoidal Oscillator Design using OTAs," MS Thesis, University of Seville, September 1987.
• Bernabe Linares Barranco, "Design of High Frequency Transconductance Mode CMOS Voltage Controlled Oscillators," PhD. Dissertation, University of Seville, July, 1990. (PDF 24.5M, 188 pages)
• Bernabe Linares-Barranco, "Analog Neural Networks VLSI Implementations," PhD. Dissertation, Texas A&M University, College-Station, Texas, USA, December, 1991. (PDF 5.5M, 350 pages)

Personal Reports:

• Bernabe Linares Barranco, "Comparing the Traditional Oscillator Amplitude Control Loop (with zero) and Li-Tsividis's Direct-Q Control Loop," Personal Report, April, 2002. (PDF 56 KB, 9 pages)

  Supervision of Theses:

• Teresa Serrano-Gotarredona, "VLSI Neural Categorizers," Univ. of Sevilla, 1996.
• Alejandro Linares-Barranco, "Study and Evaluation of Interfaces for interconnecting Neuromorphic System with AER", Univ. of Sevilla, 2003.
• Rafael Serrano-Gotarredona, "Bio-inspired AER based Architecture for Image Convolution in Real-Time," Univ. of Sevilla, 2007.
• Luis Camuñas-Mesa, "AER Convolution chips for Neocortical Asynchronous Processing of Event Coded Visual Sensory Information," Univ. of Sevilla, 2010. (pdf)
• Juan A. Leñero-Bardallo, "Study, Design, Implementation and Test of Spatial and Temporal Contrast Sensing Vision VLSI Retinas," Univ. of Sevilla, 2010. (pdf)
• José A. Pérez-Carrasco, "A Simulation Tool for Building and Analyzing Complex Hierarchically Structured AER based Systems for Visual Event-Driven Processing," Univ. of Sevilla, 2011. (pdf)
• Carlos Zamarreño-Ramos, "Modular and Scalable Implementation of AER Neuromorphic Systems," Univ. of Sevilla, 2011. (pdf)

Instituto de Microelectrónica de Sevilla   IMSE-CNM-CSIC , Av. Americo Vespucio s/n  41092  Sevilla , Spain	Tel.: + 34 95 4466666  Fax.: + 34 95 4466600  E-Mail:

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Last updated:  April 10, 2013.