(Supported by the EU Horizon 2020 Programme (REF. 687299)
(Supported by the Spanish Ministry of Science and Innovation with support from European Regional Development Fund under contract TEC2010-14285/MIC)
SIMSIDES can be used for the simulation of any arbitrary Sigma-Delta modulator, implemented with both discrete-time and continuous-time circuit techniques, including their main circuit error mechanisms which are efficiently modeled using C-MEX S-functions in MATLAB/SIMULINK. These models are grouped into a number of SIMULINK libraries and sub-libraries which can be easily opened by browsing through SIMSIDES graphical user interface. In addition to the model libraries themselves, SIMSIDES includes also some additional libraries with examples of the most commonly used modulator topologies, considering both low-pass and band-pass modulators, single-loop and cascade architectures, single-bit and multi-bit quantization, different circuit techniques, etc.
SIMULINK Block Set for the high-level simulation and synthesis of wireless receivers in MATLAB/SIMULINK
The toolbox includes a SIMULINK library with the main RF circuit models that are needed to implement wireless receivers, namely: low noise amplifiers, mixers, oscillators, filters and programmable gain amplifiers. There is also a library including other blocks like the antenna, duplexer filter and RF switches, required to implement reconfigurable architectures. Behavioral models of building blocks include the main ideal functionality as well as the most critical error mechanisms.
This research activity carried has been focused on the design of Sigma-Delta Modulators (SDMs) intended for next-generation mobile communications and software defined radio. Some recent chips recently designed are the following:
-A 90-nm CMOS 100kHz-10MHz BW, 78-to-52 dB DR, 4.6-to-11mW Flexible SC Sigma-Delta Modulator (presented at the 2010 IEEE European Solid-State Circuits Conference, ESSCIRC)
-A 90-nm CMOS Power-Scalable Concurrent Cascade 2-2-2 SC Sigma-Delta Modulator for Software Defined Radio (presented at the 2012 IEEE International Symposium on Circuits and Systems, ISCAS)
Adaptive/Reconfigurable Nanometer CMOS Low-Noise Amplifiers (LNAs) for multi-standard wireless transceivers.
This chip is part of a research line which focuses on the systematic design of adaptive, reconfigurable analog and RF CMOS ICs and systems for multi-standard wireless transceivers and next-generation software-defined-radio based mobile terminals. The main activities carried out are intended for the development of highly programmable analog front-end suitable for Software-Defined Radio (SDR) receivers, based on an extensive use of digitally-assisted RF circuits, with minimized system complexity, maximization of shared building blocks, high robustness to circuit imperfections and reduced power consumption.