Some Recent Research Projects

NeuRAM3: Neural Computing Architectures in Advanced Monolithic 3D-VLSI Nano-Technologies


(Supported by the EU Horizon 2020 Programme (REF. 687299)

FENIX-SDR: Flexible Nanometer CMOS Analog Integrated Circuits for the Next Generation of Software-Defined-Radio Mobile Terminals


(Supported by the Spanish Ministry of Science and Innovation with support from European Regional Development Fund under contract TEC2010-14285/MIC)


EDA/CAD Tools and Design Methodologies

SIMSIDES: A Time-Domain Behavioral Simulator for Sigma-Delta Modulators in MATLAB/SIMULINK

SIMSIDES can be used for the simulation of any arbitrary Sigma-Delta modulator, implemented with both discrete-time and continuous-time circuit techniques, including their main circuit error mechanisms which are efficiently modeled using C-MEX S-functions in MATLAB/SIMULINK. These models are grouped into a number of SIMULINK libraries and sub-libraries which can be easily opened by browsing through SIMSIDES graphical user interface. In addition to the model libraries themselves, SIMSIDES includes also some additional libraries with examples of the most commonly used modulator topologies, considering both low-pass and band-pass modulators, single-loop and cascade architectures, single-bit and multi-bit quantization, different circuit techniques, etc.



Related publications:

  • J. Ruiz-Amaya, J.M. de la Rosa et al.: "High-Level Synthesis of Switched-Capacitor, Switched-Current and Continuous-Time ∑Δ Modulators Using SIMULINK-based Time-Domain Behavioral Models," IEEE Trans. on Circuits and Systems I: Regular Papers, vol. 52, pp. 1795-1810, Sept. 2005.
  • José M. de la Rosa and Rocío del Río: CMOS Sigma-Delta Converters: Practical Design Guide, Wiley-IEEE Press, 2013.

SIMULINK Block Set for the high-level simulation and synthesis of wireless receivers in MATLAB/SIMULINK

The toolbox includes a SIMULINK library with the main RF circuit models that are needed to implement wireless receivers, namely: low noise amplifiers, mixers, oscillators, filters and programmable gain amplifiers. There is also a library including other blocks like the antenna, duplexer filter and RF switches, required to implement reconfigurable architectures. Behavioral models of building blocks include the main ideal functionality as well as the most critical error mechanisms.



Related publications:

  • A. Morgado, R. del Río and J.M. de la Rosa: "A SIMULINK Block Set for the High-Level Simulation of Multistandard Radio Receivers," Proc. of the 2007 IEEE Int. Symposium on Circuits and Systems (ISCAS), pp. 2950-2953.
  • A. Morgado, R. del Río and J.M. de la Rosa: "A SIMULINK Block Set for the High-Level Simulation of Multistandard Radio Receivers," Integration the VLSI Journal, vol. 41, pp. 269-280, 2008.


Some Chip Examples

This research activity carried has been focused on the design of Sigma-Delta Modulators (SDMs) intended for next-generation mobile communications and software defined radio. Some recent chips recently designed are the following:

-A 90-nm CMOS 100kHz-10MHz BW, 78-to-52 dB DR, 4.6-to-11mW Flexible SC Sigma-Delta Modulator (presented at the 2010 IEEE European Solid-State Circuits Conference, ESSCIRC)

-A 90-nm CMOS Power-Scalable Concurrent Cascade 2-2-2 SC Sigma-Delta Modulator for Software Defined Radio (presented at the 2012 IEEE International Symposium on Circuits and Systems, ISCAS)











Related publications:

  • A. Morgado, R. del Río, J.M. de la Rosa: “High-Efficiency Cascade Sigma-Delta Modulators for the Next Generation Software-Defined Radio Mobile Systems,” IEEE Trans. on Instrumentation and Measurement, vol. 61, pp. 2860-2869, November 2012.
  • A. Morgado, R. del Río, J.M. de la Rosa, Nanometer CMOS Sigma-Delta Modulators for Software-Defined Radio, Springer 2011.
  • A. Morgado, R. del Río, J.M. de la Rosa, L. Bos, J. Ryckaert and G.V. der Plas: “A 100kHz-10MHz BW, 78-to-52dB DR, 4.6-to-11mW Flexible SC ΣΔ Modulator in 1.2-V 90-nm CMOS,” Proc. of the 2010 European Solid-State Circuits Conference (ESSCIRC), Sevilla, Spain, September 2010.


Adaptive/Reconfigurable Nanometer CMOS Low-Noise Amplifiers (LNAs) for multi-standard wireless transceivers.


This chip is part of a research line which focuses on the systematic design of adaptive, reconfigurable analog and RF CMOS ICs and systems for multi-standard wireless transceivers and next-generation software-defined-radio based mobile terminals. The main activities carried out are intended for the development of highly programmable analog front-end suitable for Software-Defined Radio (SDR) receivers, based on an extensive use of digitally-assisted RF circuits, with minimized system complexity, maximization of shared building blocks, high robustness to circuit imperfections and reduced power consumption.










Related publications:

  • E.C. Becerra-Alvarez, F. Sandoval-Ibarra and J.M. de la Rosa: “Flexible Nanometer CMOS Low-Noise Amplifiers for the Next-Generation Software-Defined-Radio Mobile Systems”. Chapter in Integrated Circuits for Analog Signal Processing, Springer 2013.
  • E.C. Becerra-Alvarez, F. Sandoval-Ibarra and J. M. de la Rosa: “Design Considerations and Experimental Characterization Results of Continuously-Tuned Reconfigurable CMOS LNAs”. Proc. of the 2011 IEEE International Symposium on Circuits and Systems (ISCAS), Río de Janeiro, Brazil, May 2011.