This research line focuses on the systematic design of adaptive, reconfigurable analog and RF CMOS integrated circuits and systems for multi-standard wireless transceivers and next-generation software-defined-radio based mobile terminals.
The main activities carried out in this research topics can be grouped into two main categories:
- Development of highly programmable analog front-end suitable for SDR receivers, based on an extensive use of digitally-assisted RF circuits, with minimized system complexity, maximization of shared building blocks, high robustness to circuit imperfections and reduced power consumption.
- Design, implementation and experimental characterization of reconfigurable analog/RF ICs using nanometer (65-45nm) CMOS technologies, capable of being continuously tunable and adaptable to a variable set of radio environment parameters, standard specifications, signal conditions and battery status.
The research activities carried out in the last years have been focused on the design of adaptive/reconfigurable nanometer CMOS LNAs for multi-standard wireless transceivers. In these topics, the following IC prototypes have been designed, fabricated and tested:
- A 1-V 90-nm CMOS Continuously-Tuned Two-stage Inductively-degenerated Common-Source LNA (presented in the 2009 IEEE Int. Symposium on Circuits and Systems, ISCAS)
- A 1-V 90-nm CMOS Adaptive Folded-Cascode LNA for Beyond-3G wireless hand-held devices (presented in the 2010 IEEE Int. Midwest Symposium on Circuits and Systems, MWSCAS)
The design activities are being supported and fueled by suitable design methodologies and CAD tools, specifically developed to systematize the synthesis and verification procedure and to optimize the performance of RF circuits and systems in terms of their target specifications with minimized power consumption. A good example is a SIMULINK block set specifically developed for the behavioral modeling and high-level simulation of RF receiver front-ends.
