CMOS Processes Mismatch Characterization Consulting Service

The mismatch group at the National Microlectronics Center (IMSE - CNM - CSIC) has developed a CMOS process mismatch characterization methodology, which allows to predict and simulate transistor mismatch behavior as a function of its width and length. The method does not require special equipment (no expensive probing setups), but only a computer and a precise means for measuring I/V curves.

This simple mismatch characterization methodology turned out to be fairly robust and efficient. As a result, IMSE has developed a new mismatch model, which predicts transistor mismatch for any transistor size and with better precision than other models reported in the open literature (See references, below).

IMSE offers its expertize and software to world wide companies, institutions and universities interested in having a good transistor mismatch characterization of the VLSI processes they use. The mismatch characterization procedure involves several steps, as described below, that can be separately contracted.

The different steps of the mismatch characterization procedure are:

STEP 1: Chip Design

Design of a special purpose chip to measure CMOS transistor mismatch behavior for a wide variety of transistor sizes (typically 30). This allows to sample the transistor sizing design space (1/W, 1/L).

A special purpose chip is designed, containing an array of identical cells. Each cell contains different NMOS and PMOS transistors of different sizes (typically 30). A special decoding circuitry technique allows to access individually each transistor from the same sensing pins. A conventional I/V measuring instrument is required. The chip contains several thousands of transistors, which are typically measured in 20-30 hours.

STEP 2: Intensive Measurements

Measurement of a minimum set of I/V curves per transistor pair, which allows to predict transistor mismatch for a wide range of biasing points. This step is quite time consuming. One chip requires around 24 hours to be measured. To characterize mismatch, only a small number of chips is required (typically around 10). Optionally, mismatch chips can be fabricated periodically to monitor the corners of the process mismatch behavior.

Measured mismatch current (in %) for 30 NMOS transistor pairs of minimum size. The procedure requires to measure 4 different mismatch curves per transitor (two in ohmic and two in saturation).

STEP 3: Data Processing

A MATLAB based software is provided which performs the following functions.

1) For each measured chip, extraction of a minimum set of mismatch parameters that fully characterize mismatch behavior for a wide range of biasing points. These mismatch parameters correspond to a new mismatch model developed at IMSE (see references below), which greatly improves mismatch prediction capability with respect to previously reported models.

Measured versus predicted standard deviation of transistor mismatch current, in %. Six sub-windows are shown, each for a different transitor width W. In each sub-window there are five curves, each for a different transistor length L. The curves are obtained by setting the drain-to-source voltage V_DS to 5V, and sweeping gate-to-sorce voltage V_GS from 1.5V to 5V. Red lines are predicted curves using the IMSE transistor mismatch model (see references below), and symbols are measured standard deviations.

2) For all measured chips, computation of statistical parameters to predict behavior of mismatch parameters as a function of transistor sizing.

Measured standard deviation of mismatch in parameter 'beta', as a function of transistor width and length. For each size, there are 8 diamonds. Each diamond is the measured standard deviation for a given chip. The software provides a fitting surface which allows to predict mismatch for any size in the whole sizing domain {[1/W_min,0] [1/L_min, 0] }.

Same as previous figure, but now the correlation coefficient between 'beta' and 'threshold voltage' is shown.

Monitoring mismatch spread is convenient to identify the corners for the VLSI process. This figure shows the same curves than in the MATLAB figure in STEP 3, but for different chips. Each sub-window is for a given size, but for several chips. Symbols are measured data, and continuous lines show the average , minimum and maximum curves.

STEP 4: Simulation

Implementation of the model in standard electrical circuit simulators (Hspice) to predict transistor mismatch as a function of length and width.

To request pricing options send e-mail to mismatch@imse.cnm.es , or contact

Juan Ramos Martos
Ed. CICA, Av. Reina Mercedes s/n
41012 Sevilla, Spain
Phone: 34-95-505-6670 or 34-95-505-6666
Fax: 34-95-505-6686
E-mail: jramos@imse.cnm.es

REFERENCES:

Teresa Serrano-Gotarredona and Bernabé Linares-Barranco, "A New 5-Parameter MOS Transistor Mismatch Model," IEEE Electron Device Letters, vol. 21, No. 1, pp. 37-39. January 2000. (PDF 144K, 3 pages)

Teresa Serrano-Gotarredona and Bernabé Linares-Barranco, "Systematic Width-and-Length Dependent CMOS Transistor Mismatch Characterization and Simulation," Analog Integrated Circuits and Signal Processing, Kluwer Academic Publishers, December 1999. (PDF 1.4M, 26 pages)

T. Serrano-Gotarredona and B. Linares-Barranco, "A 5-Parameters Mismatch Model for Short Channel MOS Transistors," Proceedings of the 1999 European Solid State Circuits Conference (ESSCIRC99), pp. 440-443, 1999. (PDF 266K, 4 pages)