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Teresa Serrano Gotarredona (personal page)

For MATLAB Codes of ART1, ARTMAP, Fuzzy-ART and Fuzzy-ARTMAP algorithms of the book "Adaptive Resonance Theory Microchips", click here

Teresa Serrano-Gotarredona was born in Cordoba (Spain) in 1969. She received the B.S. degree in electronic physics in June 1992 from the University of Seville , Sevilla, Spain. She received the Ph.D degree in VLSI neural categorizers from the University of Seville in December 1996, after completing all her research at the Analog Design Department of the National Microelectronics Center (CNM), Sevilla, Spain. From September 1996 until August 1997, she obtained an M.S. degree in the Department of Electrical and Computer Engineering of the Johns Hopkins University , Baltimore, MD, where she was sponsored by a Fulbright Fellowship. She was assistant professor in the University of Seville in the Electronics and Electromagnetism Department from September 1998 until June 2000. Presently she is a Tenured Scientist at the National Microelectronics Center , (IMSE-CNM-CSIC ) Sevilla , Spain .

Her research interests include analog circuit design of linear and nonlinear circuits, VLSI neural based pattern recognition systems, VLSI implementations of neural computing and sensory systems, VLSI electrical parameter characterization, and high order CNN VLSI design.

She is currently secretary of the Sensory Systems Technical Committee of the IEEE Circuits and Systems Society.

Dr. Serrano-Gotarredona was corecipient of the 1995-96 IEEE Transactions on VLSI Systems Best Paper Award for the paper "A Real-Time Clustering Microchip Neural Engine". She has also been co-recipient of the 2000 IEEE Transactions on Circuits and Systems Darlington Award for the paper "A General Translinear Principle for Subthreshold MOS Transistors".She is co-author of the book " Adaptive Resonance Theory Microchips ".

Publications:

Books:

T. Serrano-Gotarredona, B. Linares-Barranco and Andreas G. Andreou , Adaptive Resonance Theory Microchips, Kluwer Academic Publishers, 1998. ISBN: 0-7923-8231-5 (Table of Contents -PostScript 28K-), (Preface - PostScript 58K-) , (Ordering Information). [To obtain the MATLAB codes of Appendix A (ART1, Fuzzy-ART, ARTMAP, Fuzzy-ARTMAP), click here ] This book is also being promoted by ` The MathWorks '.
T. Serrano-Gotarredona and B. Linares-Barranco, "ART1 and ARTMAP VLSI Circuit Implementations," in Learning on Silicon. Adaptive VLSI Neural Systems, G. Cauwenberghs and M. Bayoumi (Eds.). Boston: Kluwer Academic Publishers, pp. 163-192, 1999. (Ordering Information)
T. Serrano-Gotarredona and B. Linares-Barranco, "Adaptive Resonance Theory Microchips," in Innovations in ART Neural Networks: Design and Applications, L.C.Jain (Ed.), CRC Press, 1999.
T. Serrano-Gotarredona, R. Serrano-Gotarredona and B. Linares-Barranco, "Log-Domain Circuit Techniques for Nonlinear Neural Networks with Complex Dynamics," Ch. 14 in Smart Adaptive Systems on Silicon, M. Valle (Ed.). Dordrecht: Kluwer Academic Publishers, pp. 229-251, 2004.
Teresa Serrano-Gotarredona and Bernabé Linares-Barranco, "The Active-Input Regulated-Cascode Current Mirror," IEEE Transactions on Circuits and Systems (Part I): Fundamental Theory and Applications , vol. 41, No. 6, pp. 464-467, June 1994. (gziped PostScript 457K, 4 pages)
Teresa Serrano-Gotarredona and Bernabé Linares-Barranco, "A Modular Current-Mode High-Precision Winner-Take-All Circuit," IEEE Transactions on Circuits and Systems (Part II):Analog and Digital Signal Processing , vol. 42, No. 2, pp. 132-134, February 1995. (gziped PostScript 457K, 3 pages)
Teresa Serrano-Gotarredona and Bernabé Linares-Barranco, "A Modified ART1 Algorithm more suitable for VLSI Implementations," Neural Networks, vol. 9, No. 6, pp. 1025-1043, 1996. (gziped PostScript 2.0M, 19 pages)
Teresa Serrano-Gotarredona and Bernabé Linares-Barranco, "A Real-Time Clustering Microchip Neural Engine," IEEE Transactions on VLSI Systems, vol. 4, No. 2, pp. 195-209, June 1996. (PDF 2.2M, 16 pages)
Teresa Serrano-Gotarredona and Bernabé Linares-Barranco, "A High-Precision Current-Mode WTA-MAX Circuit with Multi-Chip Capability," IEEE Journal on Solid-State Circuits, vol. 33, no. 2, pp. 280-286, February 1998.(PDF 191K, 7 pages)
Teresa Serrano-Gotarredona and Bernabé Linares-Barranco, "An ART1 Microchip and its use in Multi-ART1 Systems," IEEE Transactions on Neural Networks, vol. 8, No. 5, pp. 1184-1195, September 1997. (gziped PostScript 1.8M, 11 pages)
Teresa Serrano-Gotarredona , Bernabé Linares-Barranco, and Andreas G. Andreou, "A General Translinear Principle for Subthreshold MOS Transistors," IEEE Trans. Circuits and Systems I, May 1999. (PDF 335K, 10 pages) {This paper received the 2000 IEEE Trans. on Circuits and Systems Darlington Award}.
Teresa Serrano-Gotarredona and Bernabé Linares-Barranco, "A 7-Decades Tuning Range CMOS OTA-C Sinusoidal VCO", Electronics Letters , vol. 34, No. 17, pp. 1621-1622, 20th August 1998. (gziped PostScript 69K, 4 pages)
Teresa Serrano-Gotarredona , Bernabé Linares-Barranco, and Andreas G. Andreou, "Very Wide Range Tunable CMOS/Bipolar Current Mirrors with Voltage Clamped Input," IEEE Trans. Circuits and Systems (Part II): Analog and Digital Signal Processing, to be published in 1999. (gziped PostScript 192K, 17 pages)
Teresa Serrano-Gotarredona and Bernabé Linares-Barranco, "Systematic Width-and-Length Dependent CMOS Transistor Mismatch Characterization and simulation," Analog Integrated Circuits and Signal Processing, Kluwer Academic Publishers, pp. 271-296, December 1999. (PDF 1.4M, 26 pages)
Teresa Serrano-Gotarredona , Andreas G. Andreou, and Bernabé Linares-Barranco, "Address-Event-Representation Image Filtering Architecture for Vision Processing Systems," IEEE Trans. Circuits and Systems (Part II): Analog and Digital Signal Processing, to be published in 1999. (PDF 148K, 14 pages).
T. Serrano-Gotarredona and A. Rodriguez-Vazquez, "On the Design of Second-Order Dynamics Reaction-Diffusion CNNs". Journal of VLSI Signal Processing Systems for Signal, Image and Video Technology, Kluwer Academics Publishers, November 1999 . (PDF 672K, 21 pages).
Teresa Serrano-Gotarredona , Bernabé Linares-Barranco, and Andreas G. Andreou, "Bipolar/CMOS Current-Source Flip-Flop for Application in Neuro-Fuzzy Systems," Electronics Letters, vol. 35, No. 16, pp. 1326-1328, 5th August 1999. (PDF 223K, 3 pages).
Teresa Serrano-Gotarredona and Bernabé Linares-Barranco, "A New 5-Parameter MOS Transistor Mismatch Model," IEEE Electron Device Letters, January 2000. (PDF 144K, 3 pages).
Teresa Serrano-Gotarredona and Bernabé Linares-Barranco, " A Programmable VLSI Filter Architecture for Application in Real Time Vision Processing Systems," International Journal of Neural Systems, Special Issue on New Trends in Neural Network Implementations (invited), 2000. (PDF 585K, 12 pages)
Teresa Serrano-Gotarredona and Bernabé Linares-Barranco, "Current mode fully programmable piece-wise linear block for neuro fuzzy applications," IEE Electronics Letters , vol. 38, No. 20, September 2002, pp. 1165-1166. (PDF 310K, 2 pages)
Bernabé Linares-Barranco, Teresa Serrano-Gotarredona, J. Ramos-Martos, J. Ceballos-Caceres, J. M. Mora, and A. Linares-Barranco, "Precise 90º Quadrature Current-Controlled Oscillator Tunable between 50-130MHz," Electronics Letters, vol. 39, No. 11, pp. 823-825, 29th May 2003. (PDF 438K, 3 pages)

Bernabé Linares-Barranco and Teresa Serrano-Gotarredona, "On the Design and Characterization of Femtoampere Current-Mode Circuits," IEEE Journal of Solid-State Circuits, vol. 38, No. 8, pp. 1353-1363, August 2003. (PDF 797K, 10 pages)
Bernabé Linares-Barranco, Teresa Serrano-Gotarredona, Rafael Serrano-Gotarredona, and Clara Serrano-Gotarredona, "Current-Mode Techniques for Sub-Pico Ampere Circuit Design," Int. Journal of Analog Integrated Circuits and Signal Processing, vol. 38, pp. 103-119, 2004. (PDF 417K, 17 pages)
Bernabé Linares-Barranco, Teresa Serrano-Gotarredona, and Rafael Serrano-Gotarredona, "Compact Low-Power Calibration Mini-DACs for Neural Massive Arrays with Programmable Weights," IEEE Trans. on Neural Networks, vol. 14, No. 5, pp. 1207-1216, September 2003 (PDF 1.28M, 10 pages) .
Teresa Serrano-Gotarredona and Bernabé Linares-Barranco, "Log-Domain Implementation of Complex Dynamics Reaction-Diffusion Neural Networks," IEEE Trans. on Neural Networks , vol. 14, No. 5, pp. 1337-1355, September 2003 (PDF 3.90M, 19 pages)
Bernabé Linares-Barranco, Teresa Serrano-Gotarredona, Juan Ramos-Martos, Joaquin Ceballos-Caceres, Jose Miguel Mora, and Alejandro Linares-Barranco, "A Precise 90º Quadrature OTA-C Oscillator Tunable in the 50-130 MHZ Range," IEEE Trans. on Circuits and Systems, Part I , vol. 51, No. 4, pp. 649-663, April 2004 (PDF 609K,15 pages)
Teresa Serrano-Gotarredona and Bernabé Linares-Barranco, "A Low-Power Current Mode Fuzzy-ART Cell," IEEE Trans. on Neural Networks , November 2006. (PDF 501K, 8 pages) .
R. Serrano-Gotarredona, T. Serrano-Gotarredona, A. Acosta-Jimenez, and B. Linares-Barranco, "A Neuromorphic Cortical-Layer Microchip for Spike-Based Event Processing Vision Systems," IEEE Trans. Circuits and Systems, Part-I: Regular Papers, vol. 53, No. 12, pp. 2548-2566, December 2006. (PDF, 4.3M, 19 pages).
F. Bahmani, T. Serrano-Gotarredona and E. Sanchez-Sinencio, "An Accurate Automatic Quality-Factor Tuning Scheme for Second-Order LC Filters," IEEE Trans. on Circuits and Systems, part I: Regular paper, vol. 54, No. 4, April 2007. (PDF).
J. Costas-Santos, T. Serrano-Gotarredona, R. Serrano-Gotarredona and B. Linares-Barranco, "A Spatial Contrast Retina with On-chip Calibration for Neuromorphic Spike-Based AER Vision Systems," IEEE Trans. Circuits and Systems, Part-I: Regular Papers, Vol. 54, No. 7, pp. 1444-58, July 2007.
Bernabe Linares-Barranco and Teresa Serrano-Gotarredona, "On an Efficient CAD Implementation of the Distance Term in Pelgrom's Mismatch Model," IEEE Trans. on CAD , vol. 26, No. 8, pp. 1534-1538, August 2007. (PDF 216K, 5 pages)
R. Serrano-Gotarredona, L. Camuñas-Mesa, T. Serrano-Gotarredona, J. A. Leñero-Bardallo, and B. Linares-Barranco, "The Stochastic I-Pot: A Circuit Block for Programming Bias Currents," IEEE Trans. Circuits and Systems, Part-II: Brief Papers, vol. 54, No. 9, pp. 760-764, September 2007. (PDF 252K, 5 pages).

R. Serrano-Gotarredona, T. Serrano-Gotarredona, A. Acosta-Jimenez, C. Serrano-Gotarredona, J. A. Perez-Carrasco, A. Linares-Barranco, G. Jimenez-Moreno, A. Civit-Ballcels, and B. Linares-Barranco, "On Real-Time AER 2D Convolutions Hardware for Neuromorphic Spike Based Cortical Processing," IEEE Trans. on Neural Networks, in Press. June 2008. (PDF 7.7M, 24 pages) .
J. A. Leñero-Bardallo, T. Serrano-Gotarredona, and B. Linares-Barranco, "A Calibration Technique for Very Low Current and Compact Tunable Neuromorphic Cells. Application to 5-bit 20nA DACs," IEEE Trans. Circuits and Systems, Part-II: Brief Papers, vol. 55, no. 6, pp. 522-526, June 2008.
G. Vicente-Sánchez, J. Velarde-Ramírez, T. Serrano-Gotarredona, and B. Linares-Barranco, “A Weak-to-Strong Mismatch Model for Analog Circuit Design,” Int. Journal of Analog Integrated Circuits and Signal Processing, vol. 59, pp. 325-340, 2009.
Rafael Serrano-Gotarredona, M. Oster, P. Lichteiner, A. Linares-Barranco, R. Paz-Vicente, F. Gomez-Rodriguez, L. Camuñas-Mesa, R. Berner, M. Rivas, T. Delbruck, C. S. Liu, P. Halfinger, G. Jimenez-Moreno, A. Civit, T. Serrano-Gotarredona, A. Acosta-Jiménez, and B. Linares-Barranco, “CAVIAR: A 45K-neuron 5M-synapse 12G-connections/second AER hardware sensory-processing-learning-actuating system for high-speed visual object recognition and tracking,” IEEE Trans. on Neural Networks, vol. 20, no. 9, pp. 1417-1438, September 2009.
R. Serrano-Gotarredona, M. Oster, P. Lichtsteiner, A. Linares-Barranco, R. Paz- Vicente, F. Gómez-Rodríguez, H. Kolle Riis, T. Delbrück, S. C. Liu, S. Zahnd, A. M. Whatley, R. Douglas, P. Häfliger, G. Jimenez-Moreno, A. Civit, T. Serrano-Gotarredona, A. Acosta-Jiménez, B. Linares-Barranco, "AER Building Blocks for Multi-Layer Multi-Chip Neuromorphic Vision Systems," Advances in Neural Information Processing Systems 18, Y. Weiss and B. Scholkopf and J. Platt (Eds.), MIT Press, Cambridge, MA, 2006. (PDF 923K, 8 pages) .
L. Vancaillie, F. Silveira, B. Linares-Barranco, T. Serrano-Gotarredona, D. Flandre, " MOSFET mismatch in weak/moderate inversion: model needs and implications for analog design", Proc. of the 2003 European Solid State Circuits Conference, (ESSCIRC'03), pp. 671-674, September 2003. (PDF 118K, 4 pages) .
T. Serrano-Gotarredona and B. Linares-Barranco, "CMOS Mismatch Model valid from Weak to Strong Inversion", Proc. of the 2003 European Solid State Circuits Conference, (ESSCIRC'03), pp. 627-630, September 2003. (PDF 2.98M, 4 pages).
B. Linares-Barranco and T. Serrano-Gotarredona, "Reliable Handling of Fempto-Ampere Currents in Standard CMOS," Proc. of the 2002 European Solid State Circuits Conference, (ESSCIRC'02), pp. 109-112, September 2002.
T. Serrano-Gotarredona and B. Linares-Barranco, "A 5-Parameters Mismatch Model for Short Channel MOS Transistors," Proceedings of the 1999 European Solid State Circuits Conference (ESSCIRC99), pp. 440-443,1999. (PDF 266K, 4 pages) .
T. Serrano-Gotarredona, B. Linares-Barranco and Andreas G. Andreou, "MOS/Bipolar active Input Current Mirrors with 13-Decades Gain Adjustment Range," Proceedings of the 1998 European Solid State Circuits Conference (ESSCIRC98), pp. 296-299, 1998. (PDF 142K, 4 pages) .

Patents:

Teresa Serrano Gotarredona y Bernabe Linares Barranco, "Circuito para el reconocimiento y establecimiento de categorias de patrones binarios," spanish patent, registration number 9401031, publication number 2103176, 1994.
Teresa Serrano Gotarredona, "Categorizadores Neuronales en VLSI," PhD. Dissertation, University of Seville, December, 1996. (Gziped PDF) .
Teresa Serrano Gotarredona, "VLSI Implementation of a Pseudo-Gabor Filter," MS Thesis, The Johns Hopkins University, July, 1997.